To overcome the challenges yet realize the opportunities presented by semiconductor densities and capabilities, electronic product companies utilize a System-on-a-Chip (SoC) design methodology which incorporates pre-designed components, also called SoC Intellectual Property (SoC-IP).  Companies leverage these IP components and integrate their own design elements or algorithms to differentiate their products.  Typically, SoCs will incorporate processors, which allows customization in the layers of software as well as in the hardware around the processors.  However, as the number of transistors in a chip grows by a factor, the design complexity grows by an exponential of that same factor!  (i.e. twice the size is a square of the complexity)

While the challenges of creating and verifying each of the individual components in a SoC is significant enough, the task of verifying the SoC as a whole is even more challenging.  The methodology used to test multi-million gate designs has a direct effect on the chances of first pass success, schedule (i.e. time to profit) and non-recurring engineering (NRE) costs.  Relying on traditional directed test verification approaches are inadequate in this new design arena.  Advanced design verification methodologies like UVM combined with verification IP (for transactor-based verification) are required elements of any SoC development.

Multi-Disciplined Teams of People Ensure Success

Integrating a processor, digital signal processor, peripherals, memory, and control logic in addition to the application-specific embedded software requires a team of seasoned engineering professionals experienced in each discipline with an understanding of how all of these complex pieces come together into a whole product.

Couple the complexity of design with dynamics of rapidly emerging semiconductor technologies and geometries that continue to introduce challenges at both the RTL and physical design levels; and you can quickly appreciate the need for having an experienced team on your side. 

Platforms enable rapid development and product differentiation

To support adoption of advanced technology, Intrinsix has developed Platforms that provide a head start in SoC design based on assembling components to accelerate product development.  These platforms are comprised of design and verification IP that enable teams to not only assemble the components into a high-performance system but also significantly speed up verification.

Process ensures successful execution

Intrinsix starts its SoC design processes with a well-written system requirement document and a detailed hardware design specification.  We can start with your written specification, or we can write the specifications to meet your project requirements.  Writing the specifications enables our combined teams to clearly identify all of the critical aspects necessary to the success of the project.  The rigor of writing a thorough specification also helps define schedules and costs to a finer degree of accuracy and allows developers of sub-modules to proceed forward in parallel based on an agreed upon interface specification and verification plan.

Each sub-module of the SoC undergoes optimization to ensure your chip provides the maximum performance at the lowest power.  Execution speed and power consumption are directly related to the design architecture.  There are occasions where circuit area can be increased to accommodate parallel logic which will allow clock rates to be slowed down resulting in a net reduction in power consumption at no loss of performance.  There are other circumstances where raw speed is the ultimate concern, and the hardware topology must be designed to maximize that aspect of performance.

Complex FPGA Design

Field Programmable Gate Arrays are often the best end-game for today's product companies and can be your fastest path to initial product proof of concept or even full production when unit volumes are small. FPGA's can also help to reduce risk by offering real-time software debugging solutions for embedded SoC solutions.  However,  when designing even the least complex FPGAs,  care and diligence must be used to treat the design and verification process with the same rigorous approach as their custom-mask equivalents.  There is too much logic (and IP) within the FPGA to test from the pins in your lab (i.e. lack of controllability and observability) so the chip must be planned to work the first time – within the target system.

FPGA as Prototype and Software Development Tool

Intrinsix often recommends and incorporates a methodology that utilizes FPGAs as a critical component of an end-game custom SoC. Because processors enable software to run on these systems,  the sooner that thes software team can begin to boot the system and try their algorithms on real hardware,  the faster the product can get to market.  Moreover,  funding and budget cycles can be accommodated via real prototypes to prove system functionality and to tweak performance.