Intrinsix Platforms and semiconductor IP provide unique solutions that can be quickly brought to bear on customer projects. The two most direct and tangible benefits are in speeding time to market and predictability of schedule and outcome. This, in turn, drives down effective cost of development and, of course, accelerates time to revenue for Intrinsix customers.
Intrinsix platforms consist of groups of semiconductor IP which have been pre-configured for a particular market or purpose. Often, the Design IP (whether represented by RTL or transistors in a particular process) is paired with Verification IP to create a development suite for that market. A critical aspect of the Intrinsix IP strategy is that we avoid marketing our IP as standalone products. This strategy frees us from typical “Not Invented Here” attitudes and positions our solutions as agnostic in regards to IP choices. Our customer’s view of Best-in-Class price/performance wins the day. Every day. With this approach, we are able to partner with all providers of IP, such as EDA companies and boutique IP companies. New solutions and options appear all of the time and Intrinsix strategy ensures a level playing field for our customers and their choices.
Most of the Platforms and IP offered has been derived from focused internal R&D, funded solely by Intrinsix. But a significant portion also comes directly from Intrinsix participation in the Small Business Innovate Research (SBIR) program. This program funds companies to create compelling solutions for government and commercial advancement. Check out our SBIR and Patents page for a complete list.
The Intrinsix AIB PHY Intellectual Property is a complete set of hard and soft macros that provides a direct connection to the AIB heterogeneous digital interface for “Chiplet-to-Chiplet” communication. Intrinsix is providing the IP as a standalone package or it can be combined with customization (changes to the PHY) or integration (integrating the PHY in an SoC) services. Both services are outlined below. The macro contains the high-speed process dependent circuitry to minimize the effort involved in adopting the AIB interface standard. Proven macros and flows minimize the risk of achieving first pass success.
The AIB PHY utilizes a parallel synchronous interface that supports transactional and streaming adapter interfaces. An existing 3rd party interface is available to connect to AMBA AXI interconnect and IP. To support various Chiplet bump densities and technologies the microbump array is external to the PHY macro. Multiple levels of metal are left open to support the routing to the microbump array.
Base macros (Channel macro & AUX macro) available now in TSMC 16FFC and GF 14LPP processes.
Figure 2: AIB IO Cell and Channel Architecture
The following is one example of an AMBA/Tensilica SoC Development (Intrinsix IP in Dark Green)
Surrounding the Development IP is the Intrinsix Verification environment (with Verification IP on a light green background)
Intrinsix is also experienced with the bridge interface between the local Tensilica (PIF) bus and the AMBA environment
Proprietary Intrinsix AMBA Verification IP in green
See Component IP file for a detailed IP List.
Intrinsix IP Components for AMBA Based Systems
AHB Quad SPI Master / Slave
Multiprocessor Mailbox
AHB High Performance DMA
ECC for SRAM and Fabric
SPI to APB Analog Controller
AHB Master Configurable Arbiter
AHB Slave Configurable Arbiter
APB I2C/SMBus Master Controller
APB PWM Controller (8 Channel)
APB Interval Timer (3 Channel)
APB Watchdog Timer (1 Channel)
APB Real-Time Clock
AES-128, 256 Encryption
SHA-256 Authentication
MIPI Battery Interface
SENT Protocol Controller
Programmable Filtering Engine
APB ADC Controller (2 Channel)
System Manager (clks, reset, power)
JTAG Controller with DFT/MBIST
AHB Low Power DMA
APB I2S/TDM Controller
Status & Control Register Builder
AHB Quad SPI Master / Slave
Multiprocessor Mailbox
AHB High Performance DMA
ECC for SRAM and Fabric
SPI to APB Analog Controller
AHB Master Configurable Arbiter
AHB Slave Configurable Arbiter
APB I2C/SMBus Master Controller
APB PWM Controller (8 Channel)
APB Interval Timer (3 Channel)
APB Watchdog Timer (1 Channel)
APB Real-Time Clock
The following Analog and/or Mixed Signal Components (and more!) are available to Intrinsix Customers. This IP (both design and verification IP) will help decrease development time while increasing quality and reliability.
Analog Design IP
Mixed Signal Verification IP
OVERVIEW
FortrixTM is a self-contained, feature-rich IP platform which provides Root-of-Trust and cybersecurity features to chiplet based systems and standard SoCs. It’s unique combination of hardware and firmware provides NSA Suite-B and CNSA levels of performance with low power and low latency. Secure Boot, Root of Trust, Encryption/Decryption, Secure Communications, and Secure Firmware Update are among the features currently provided. CEVA has customized its security IP to meet the needs of chiplet based designs establishing a secure channel between Host and Companion chiplets to allow secure message passing, authentication, attestation, and firmware download. Take together, these features provide protection against a variety of threat vectors including; firmware copying/tampering, chiplet counterfeiting and chiplet disabling/modifying.
Main Features
Block Diagram
Pulse-width modulation (PWM) is a modulation process or technique used in most communication systems for encoding the amplitude of a signal right into a pulse width or duration of another signal, usually a carrier signal, for transmission. Although PWM is also used in communications, its main purpose is actually to control the power that is supplied to various types of electrical devices, most especially for inertial loads such as AC/DC motors.
Intrinsix has developed a number of PWM IP components that are highly reusable for new PWM designs. This will reduce engineering time and improve reliability through the reuse of proven designs.
PWM Controller Elements
Digital PWM Controller Elements
Sigma-Delta Modulation Explained
Use of a Sigma-Delta Modulation scheme in the design of Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs) allows for very efficient and/or high performance data converters. Sigma-Delta Modulation (aka SD Modulation, SDM or Delta-Sigma Modulation) is not a new technique, but has been deployed relatively recently in a wide range of applications thanks to continued advances in CMOS semiconductor technology. Intrinsix has developed several families of Sigma-Delta based IP blocks that are designed to be inserted into larger designed targeted for standard CMOS processes such as those available from TSMC, UMC, SMIC. Chartered and others.
Intrinsix Sigma-Delta Modulator Refinery
Designing a finely tuned SDM-based device, such as a data converter, can be a very time consuming effort, even by engineers very familiar with the technology. This is where Intrinsix can get you ahead of the curve. Intrinsix has developed the Intrinsix SDM Refinery, a proprietary design automation suite. When deployed by our Mixed Signal Design Team, SDM Refinery allows us to quickly produce optimized Sigma-Delta Modulators (SDMs) and SDM-based, over-sampled DACs and ADCs. Not only do the results come faster, but the components developed with the SDM Refinery are optimized far beyond what could be expected from a manual design methodology.
Some of the additional features of the refinery:
An example of some of the Sigma-Delta based Intellectual Property (created from the refinery) which are available from Intrinsix:
This platform is comprised of all components required in a highly-integrated data acquisition solution for smart sensors. It is targeted at high precision requirements such as MEMS accelerometers, gyros, pressure sensors, magnetic sensors, battery and electrical sensors, and other custom sensing applications. It includes the analog signal conditioning, analog to digital conversion, filtering, digital signal processing, control-plane processing, protocol engine and serial communications. All blocks are programmable and configurable to optimize performance to a given application, and the platform includes much of the software needed for common signal processing and serial communications.
The Data Acquisition Platform for Sensor Integration uses IP blocks which have been developed by Intrinsix and targeted into a comprehensive mixed signal solution, including analog, digital and software components.
The internet of things (IoT) is the internetworking of physical devices, vehicles (also referred to as "connected devices" and "smart devices"), buildings and other items - embedded with electronics, software, sensors, actuators, and network connectivity that enable these objects to collect and exchange data.
Intrinsix has experience and IP related to the many disciplines that compose IoT-based projects. The following graphic shows the entire range of IoT domains where Intrinsix has previously worked, and where seamless design and verification IP can be utilized to shorten new IoT design cycles, improve security and to improve probability of successful outcomes through the reuse of IP from previously successful designs. Most IoT systems will only use only a subset of these elements.
Application Areas for IoT Systems
The following list are just some of the product application areas where IoT technology will usually be applied:
ROIC Technology for Demanding Imaging Applications
New innovations in ROIC technology are available from Intrinsix - a leader in advanced imaging chip design services. The offerings address modern imager challenges such as Signal to Noise (SNR), Dynamic Range (DR), conversion efficiency (watts/bit/sec) and DC scene “skimming”. The architectures are applicable to cooled (70K) or uncooled photodiode detectors (monolithic, BSI, hybridized), and micro-bolometers (continuous or pulsed). Current offerings are briefly described below, with example size/process node data points:
Serpentine Sigma-Delta Modulator based ROICs
Per-pixel Log2ADC based Digital Focal Plane Array (DFPA)
In-pixel Correlated Double Sampling
Adaptive self-heating polynomial estimation and correction