From the very start of a chip development program, the question of foundry choice can be quickly identified as one of the most critical aspects of the process. This choice will have significant ramifications until the very end of the life-cycle of your electronic product as a critical supply chain component. Do you need onshore Trusted solutions that will be around for a decade or the cheapest, fastest, best silicon that will get you through a few years? Do you have a supply chain risk reduction strategy or do you simply need to get your first product out to the market…. tomorrow?
Many Intrinsix customers come to a development project with a pre-determined foundry choice - simplifying the task of locking and loading the design kits and tools (whether peculiar or familiar) into our design flows. Others enjoy the benefits of our independence and our discussion from the start is about choices: Intrinsix works with EVERY foundry in the semiconductor business.
Physical Design (PD) and silicon realization is where the rubber meets the road: the design gets real, the chips get built, and, typically, a great deal of money is spent in the process. Intrinsix navigates this gauntlet of transistor design, prototype development, and production finalization through its use of Platform, Process, and People.
Intrinsix maintains a significant platform of compute resources and EDA infrastructure for physical design but the critical recipe for success in physical design and silicon realization comes from its process and people.
During the RTL design completion, and as gauged by the metrics generated by the verification team, the PD team gets started by managing DFT and DFM tasks, monitoring/completing synthesis, and iterating on trial placement and layouts. The benefit of multi-functional team cooperation (whether RTL is done by Intrinsix or our customer) is that iterations, information, and progress can be guided up to and through the handoff to the PD team. Late stage PD-related changes (or in some cases market-driven RTL changes!) must be worked at all levels of abstraction in order to stay on schedule. Intrinsix engineers are well-versed in utilizing state-of-the-art tools and processes to a) insure the design comes into PD smoothly, b) gets through layout and late-stage iterations without a hitch, c) gets through the wide range of foundry-specific Design Rule Checks (DRCs), Layout vs. Schematic (LVS), and Electrical Rule Checks (ERCs) without delay. See the chart to the right for additional information on the PD process.
In the decades of design development, Intrinsix has seen it time and again: all of the schedule pressure mounts on the PD team to complete the design and get it into the foundry without missing the foundry shuttle or wafer run. However, the cool heads of experienced people and the utilization of a well-oiled process will insure that every minor rule violation is not a major misunderstanding in disguise. Intrinsix has worked with dozens of process nodes at leading and trailing edge foundries – that experience turns into the right questions at the critical moment in the sign-off process when everyone wants to know: Will it go on time and will it work?
Chips need supply chain management precision: packaging, shipping, testing, prototype bring-up, and production coordination are all interwoven and have significant impact on cost and schedule. Intrinsix works within your existing supply chain or helps create a streamlined supply chain specific to your needs. Our project management team has experience at both ends of this spectrum, from DIY to pre-ordained flows for our semiconductor customer experts.
In those cases where customers have options and want Intrinsix to manage the supply chain, we often deploy our Glass Box Supply Chain Model – providing transparency and confidence throughout the process.
Contact Intrinsix to find out more about our Glass Box Supply Chain Model.
Clock Tree Synthesis