Mixed-Signal and RF Chip design can be a challenging aspect of electronics development. Correctly judging the interplay of transistors/resistors/capacitors within a semiconductor device depends on precise models, exacting tools and processes, and a solid understanding of the physics behind today's advanced chip process nodes. In addition, bringing in the critical role of verification onto the development team early as an equal partner to the design role ensures an independent view of the correctness as derived from the functional specifications and requirements document. Finally, having critical minimum infrastructure regarding analog IP and tools is a necessary foundation of the Intrinsix Platform, Process, and People for Mixed-Signal and RF designs. The following sections highlight some of the most important aspects,
Intellectual Property in the Mixed-Signal and RF space is very important for any design team that does not want to “start from scratch” on each design. Indeed, IP at all levels of abstraction and targeted to a wide range of foundries is the hallmark of a team with decades of experience like Intrinsix. Highly configurable platforms at the market/application level, such as the ones below, provide reference and substance to designs on day one:
In addition, lower level functional IP can be combined and integrated quickly for fastest time-to-working-chips. Intrinsix maintains a long list of this critical infrastructure IP in its Mixed-Signal Jump-Start Kit for re-use and porting to new process nodes for each project.
Intrinsix has a robust Mixed-Signal development flow honed from the experience of hundreds of successful programs in both mixed-signal and digital SoC projects. (See more of our development flow in the example of our Sigma-Delta Refinery in our Platforms listings.)
Mixed-Signal design flow is a systematic approach to designing successful integrated circuits on a tight budget and schedule. Most mixed-signal projects can use this flow with minimal modification to suit the requirements of the specific application. Due to the inherent complexity of many mixed-signal development projects, adherence to a robust and proven approach maximizes the likelihood of first pass success.
reduceRF design flow leverages the Mixed-Signal approach to reduce the risk of RFIC design, especially for RFICs with significant digital content. System-wide requirements are verified first using traditional link budgets and re-verified using Chip in Package on PCB simulations. Co-Simulation between RF blocks, Analog blocks, and Digital logic is enabled using behavioral models (including critical impairments) for less-critical blocks to improve simulation times. The result is an improved confidence that the RFIC will not only meet the device specification but will work in the system in one pass.
Mixed-Signal programs present a level of complexity beyond that present in a digital-only SoC. The primary reason for this is that analog design has to deal with an infinite continuum of potential inputs and combination of inputs. Secondarily, analog performance is susceptible to degradation when digital edges are present on the same silicon substrate. Finally, mixed-signal circuits often include data transfer and/or control signals that cross the analog/digital boundary. Since errors are most likely to occur at boundaries and since the tools for analog and digital simulation reside in fundamentally different domains, there are a great many potential points of failure in a mixed-signal IC development program.
As a result of this complexity, programs which do not approach the development in a robust, systematic manner are at great risk of exceeding schedule and budget, and of failing to meet performance (or even functional) goals. The solution is to follow a known, proven design flow, with checkpoints at critical junctures, open and continuous communication with all parties, and numerous redundant opportunities to uncover missing or incomplete requirements in the specification, and to do so early. Critical in this design flow is the inclusion of a robust mixed-signal verification process.
Driving success in the complex world of analog and mixed-signal come from rapid adoption of both state-of-the-art processes (much of which originated in the digital design space, see our verification page for more info) and also constant improvement in the real-world of high pressure schedules and limited budgets. You can’t simulate everything and you can’t simulate forever. It is what you don’t know that will get you. Intrinsix drives verification at many levels of abstraction and works with customer’s specifications using high level models as a form of testing our customer’s true needs at each level. As a result, our process and devotion to hiring and training dedicated verification staff who work in parallel with our design team are key foundations for our customer’s working chips.
Intrinsix has been providing Mixed-Signal design services as a company since year 2000, but our engineers have been doing mixed-signal design since its inception at Bell Labs in the early 1980s. Our team continues to embrace new tools and technologies as they have become available and have converged around a robust flow that starts with architecture development, adds high level Simulink and MATLAB modeling to verify architecture, and then proceeds systematically with VerilogA modeling to flesh out component requirements before transistor level design begins. Our dedicated Mixed-Signal Verification engineers also engage early to create their hierarchical infrastructure specific to each new chip but building on re-used elements where possible and their career-long skills of finding problems and catching bugs before they can emerge in prototypes to cause functional and performance problems. Our Mixed-Signal and RF engineers are seasoned veterans that love new challenges and are proud of their extraordinarily successful run of working chips.
Architectual Design
Behavioral Modeling
Circuit Design & Schematic
Pre-Layout Circuit Simulation
Layout
Parasitic Extraction
Post-Layout Simulation
Monte Carlo & DFM
Full Chip Integration
Mixed-Signal Verification
