Verification is the process by which a design is checked against the specification to ensure that it satisfies all requirements. The verification process is done independent of design, most critically by separate verification experts. In the digital domain, there are established and continually improving tools, languages and methodologies to enable robust verification: OVM, UVM to name a few of the currently popular methodologies. These tools allow rapid testing of circuit response to a wide range of automatically generated inputs, and metrics such as coverage by which the completeness of the verification effort is judged.
The Intrinsix verification teams are experts in complex ASIC, SoC, FPGA and system verification. Our extensive experience in designing processor-based SoCs has allowed our teams to pioneer the development of transactor-based hardware and software verification methodologies.
Our verification team understands which tools and methods to apply at the appropriate time based upon the types of designs and application areas. We do not believe in a "one size fits all" methodology. Rather, we use appropriate tools where needed.
Intrinsix has pioneered verification methodologies which utilize transactor-based verification to dramatically accelerate the development of verification suites focused upon SoC integration.
SoC verification is defined as a problem where the whole is greater than the sum of its parts. It is not sufficient to think of a SoC as merely the interconnection of pre-verified IP. While an important aspect of SoC verification is indeed verifying the correct interconnection of the SoC building blocks, it also includes HW/SW co-verification, verification of clock, reset, power control, and DFT sub-systems, and verification of performance metrics. A SoC verification environment must integrate software development tools that enable HW/SW co-verification and bare-metal driver development. A SoC verification environment developed using a standard verification re-use methodology (such as UVM) allows for integration of reusable verification IP that is currently available for the standard interfaces found on a SoC (e.g., AMBA, PCIe, USB, Ethernet, DDR-3.) A SoC verification environment must be flexible enough to span everything from BootROM verification to post-layout gate-level simulations.
It is well proven that the cost to fix a bug increases exponentially as products move through the development cycle. Finding bugs early in the design cycle reduces the cost of fixing a bug. Early bug detection applies in particular for complex SoCs considering the high cost of a device respin or releasing new firmware to customers. Tests developed during the verification phase can be directly ported to post-silicon lab testing, reducing the amount of time needed in the lab. Inadequate verification typically results in failure. The only way to ensure first-pass success is to employ modern metrics-driven functional verification as an integral part of any SoC development.
Intrinsix engineers are experts in IP integration and SoC verification and have completed hundreds of SoC verification projects ranging from simple single processors devices to complex multi-processor devices. By deploying the Intrinsix re-usable and flexible UVM-based SoC verification platform, we can very quickly have a SoC verification environment up and running. This streamlined approach reduces overall project schedule and cost. The Intrinsix Embedded Software team works alongside the verification team to develop bare metal drivers that allow for more efficient and effective testing, and which can be ported directly to post-silicon verification testing, again reducing overall project schedule and cost. Intrinsix uses a requirement-based metrics-driven verification methodology, and thorough verification reviews with the customer, to ensure high quality of verification and first-pass silicon success.
Mixed-signal verification is the evolving practice of applying robust digital verification tools and techniques to the problem of verifying mixed-signal ICs. Because the analog portions of mixed-signal circuits operate on a continuum of voltages and frequencies, mixed-signal verification presents particular challenges. Special drivers must be developed to allow the automatic generation of analog stimulus; special monitors must be constructed by which the (often) analog response to stimulus can be captured; and pass/fail criteria must be developed which is unique to different kinds of analog circuits. Only with all three of these components (Special Drivers, Monitors and pass/fail criteria) in place can verification be automated. The verification process can also discover ambiguities in the specification, forcing resolution and agreement when it is least expensive.
Intrinsix has been at the forefront of mixed-signal verification and was an early adopter of mixed-signal verification tools. Intrinsix has developed an approach to analog modeling which significantly reduces simulation time during the verification stage while preserving the traceability of the results to actual transistor level circuits. We have a library of models we can quickly adapt to most types of analog circuits.
Intrinsix has also developed a collection of stimulus drivers which, along with measurement infrastructure for extracting critical performance parameters from simulation runs, enables automated pass/fail evaluation. With each new verification effort, the library of these stimulus and monitor blocks grows, significantly cutting the time necessary for us to develop the verification setup specific to your custom mixed-signal IC.
Verification IP (VIPs), sometimes referred to as Verification Components, are modular blocks that interact with your design to exercise the functionality that has been built. The use of already proven VIPs can shorten the verification schedule, increase the productivity of your verification team, and give a higher quality of results. VIPs can be as simple as a block that verifies that an interrupt occurs at the correct time, to exercising an interface to the standard including all error cases, to testing that all the expected DMA transfers have occurred.
Verification, as most engineers know, is a labor intensive process and can be as much as two times or more the effort of design. Most often, in a large SoC, the completion of the verification effort is the long pole in completing a design. Customers who engage in verification efforts must develop the verification test benches and the necessary components all of which requires time and expense. The alternative is to purchase VIP from 3rd party vendors and then work to understand it and integrate it which brings with it many unique challenges.
Intrinsix has developed our own Verification IP and has successfully used it on many designs to help improve schedule and reduce cost. Our VIP has been designed to increase a verification team's productivity with solutions based on re-useable V IP blocks. These cost effective solutions are available in several standard interfaces and high-level verification languages. The VIP blocks are easily controlled during testing and are configurable to match the existing test bench environment. System level scenarios are easily created and controlled. Our VIP components easily integrate into your existing test environment.
Verification Plan & Traceability
Test Bench Coding
Test Case Development
Signoff & Release