Semiconductor Design & Verification Articles

RF System Evolution

An RF system in mass production has gone through many design iterations where performance and functionality have been enhanced, and size weight or power consumption have been reduced. Typically, the life of a new wireless system begins with a prototype using commercially available components and integrated circuits. Early production designs usually replicate the prototype architecture using many of the original components. These designs are assembled from devices that were not specifically designed to work together and rarely represent an optimum in performance, cost or size. Commercial pressures to reduce cost, add functionality or significantly reduce size make an ASIC implementation desirable. In many cases, this results in an opportunity rethink and reoptimize the overall system design.

RF ASIC System Design

The optimum architecture and block performance requirements are usually quite different for an ASIC implementation compared to a discrete. In transitioning discrete RF designs to an ASIC, it is essential to start with detailed requirements for performance and functionality. The initial phase of the RFIC design usually consists of detailed system analysis. Performance parameters like operating frequency range, S/N ratios, linearity, and operating power level are defined and reviewed at equivalent points in the signal chain for the board level and the proposed ASIC replacement. This step usually results in an end to end behavioral model of the proposed ASIC. One typical result of this process is the isolation of key performance parameters that are usually driven by a small number of discrete components. Typically, sensitivity, linearity, dynamic range and phase noise are key drivers. Achieving these performance requirements with an RF ASIC friendly architecture is one of the primary system design tasks in any RF ASIC development. Once the performance and functionality requirements are defined, the RF ASIC system design can begin.

The major factors that make RF ASIC design different than discrete design are:

• The 50 Ohm Question – Internal impedances in an RF ASIC can differ significantly from 50 ohms;
• Device versus process selection – Performance and functionality need to be achieved with the capabilities of a single semiconductor process.
• Programmability, calibration, and control – RF ASICs offer significant opportunities for system optimization and performance improvement through programming and configuration.

The 50 Ohm Question

Most RF and Microwave Integrated circuits are specified to operate in a 50 ohm system. The standardization on 50 ohms goes back to the development of coax cables for radio transmitters in the 1930s. While printed circuit board and packaging technology have evolved, 50 ohms is still a good standard today to match a multilayer FR4 board to a 0.5mm fine pitch package. Internal to an ASIC, where the dimensions are measured in um or nm, there is no compelling reason to stick with the 50 ohm standard. In fact, the choice of internal impedance in an ASIC is a key design variable that drives power consumption and operating bandwidth. Consider a case where a 1V linear voltage swing is required.

It takes 20mA of current to generate 1V in a 50 Ohm system while the requirement drops all the way down to 1mA at 1kOhm. This has significant savings in power consumption. Load capacitances internal to an ASIC can be very small and well controlled. Consider the case of a 500fF load driven by various source impedances. Even with a 1kOhm impedance, a 3dB bandwidth of 2GHz can be achieved. The penalty for making this trade-off is usually S/N ratio. For example, 1V peak signal delivers +10dBm to a 50 Ohm load but only -3dBm to a 1kOhm load, a loss in signal power of 13dB. Meanwhile, the available noise power from a 50 Ohm or 1kOhm source (kTB) is the same. The key point is that inside an RF ASIC, all the source and load impedances become design variables that can be chosen based on operating frequency, S/N ratios, linearity requirements, and overall system performance. It is not unusual to have the external RF interfaces matched to 50 ohms while internal impedances are tailored to optimize performance as the signal propagates through the chain. At frequencies up to say 1GHz, a 300 Ohm reference impedance is practical, and transmission lines can be non 50 ohms well into the mm-wave range.

Life Beyond 50 Ohms

The simple concept that most of RF ASIC signal chain can be a non 50 ohms has some profound implications. First, there is a significant and obvious opportunity for power consumption reduction. Gain control algorithms, dynamic range, noise levels, and compression characteristics can all be analyzed and reoptimized with respect to these new system impedances. Given that transistors and logic cells are essentially free on an RF ASIC, there are opportunities for signal detection, performance boost, and power saving modes that enhance performance in the presence of interferers or lower the average power consumption. Freed from the 50 Ohm paradigm subsequent blogs will look at:

• Process Selection - process capabilities versus discrete device selection.
• Performance trade-offs of "on-chip" versus "off-chip" components and active matching versus passive matching.
• System level performance optimization using on-chip calibration, correction, and control.