Pre-Silicon Software Execution and Performance Validation – A Case Study
In a persistent trend, shrinking IC geometries and higher levels of integration are leading to SoCs packed with increasingly...
Verifying SoC BootROM Using Standard Verification Techniques
BootROM code is omnipresent in modern System-on-Chip (SoC) ASICs. While verification strategies for RTL are well established...
Modeling Strategies for a Buck DC-DC Converter
Strategies for comprehensively simulating an ASIC often require multiple models for the same block in the design. Each model...
Why Formal Verification Should Be Part of Your Verification Plan
Designing an ASIC that is free of functional bugs is an important requirement for first spin success. Yet as designs grow...
The Post GDS Nightmare
As tapeout approaches, did you ever have that nagging feeling that there must be something you forgot? Did you miss the latest...
Why Use-Cases Are Critical in SoC Verification
Verifying the correct behavior of small functional blocks and simple IP on a SoC is largely a solved problem. Techniques for...
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