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Semiconductor Design & Verification Articles

The Post GDS Nightmare

As tapeout approaches, did you ever have that nagging feeling that there must be something you forgot? Did you miss the latest ROM code updates? Have all active circuit die edge clearances been checked? Was the IR drop analysis run on the latest database? There's a lot to remember. And when IC mask and fabrication costs exceed half a million dollars, you can’t afford to miss anything.

Because we have been through this process hundreds of times. With over 500 design fabrications releases behind us, we've developed a series of checklists that help us avoid these nightmares. Checklists are such a simple concept, yet are shown to be remarkably effective, especially in complex domains (such as IC design) where the coordinated efforts of highly specialized teams and individuals is required. When there are thousands of steps that have to be performed to build a product, many of which are dependent on the outcome of previous steps, it's too easy to make a mistake or overlook something critical. The problem is compounded, especially in pressure situations, when deadlines loom.

Atul Gawande, MD, author of The Checklist Manifesto writes that these mistakes are made even by the most highly skilled, competent professionals. They’re a byproduct of the incredibly complex nature of the work. His book outlines the proven benefits of using checklists during surgery, but the same arguments apply equally well to custom IC design.

post gds nightmare when releasing a chip to manufacturingThe final chip release checklists that we have developed cover all aspects of the IC development process – from the specifications to the design rule checks on final chip layout. Each checklist constitutes a gate to the release – all items must be reviewed and completed before the release can proceed. By carefully working through each item on the checklist, we can guarantee that all critical details have been addressed before tapeout.

We manage the checklists by dividing them into ten different categories that cover various aspects of the release process. For example, there are checklists for analog design, analog layout, packaging, design for test, design rule checks, and so on. Each checklist will have an owner, responsible for reviewing and obtaining sign off on each item in the list.

The checklists have evolved over time; each one encapsulates the accumulated experiences of scores of our engineers working through hundreds of custom IC designs, from the initial steps of RTL creation, though verification, physical design, and tapeout. The checklists embody valuable knowledge and experience that has been accumulated over time; and are viewed as important pieces of our intellectual property. They have become an integral part of the process, serving as key milestones along the path toward tapeout.

Some examples will make clear just how much detail is embodied in these checklist items. For example, the following are examples of elements that must be satisfied by designs with analog content:
  • Verify that a full chip level floating node check was run on both the digital and analog blocks.
  • Verify that all devices near power domain boundaries have the required latch-up protection rings.

The digital design checklist includes items like the following:

  • Check that spare cells were added to the design (to simplify design modifications).
  • Review synthesis logs for errors and warnings.

The digital layout checklist includes:

  • Check that the design rule checker (DRC) was run on the layout and that the option to perform density and antenna checks was enabled.
  • Check that all DRC errors, warnings, and flags are manually reviewed, and each one documented.
  • Verify that static timing analysis was run after final metal fill.
  • Check that layout versus schematic (LVS) checking did not include any black boxed instances.

These are just a tiny fraction of the total number of items on the checklists. Each item reflects a detailed step that must be taken in one particular area of expertise. The digital layout specialist is not likely to know what has to be done on analog sections of the design, and the digital design engineer probably doesn't know what has to be done for layout. Furthermore, the sheer number of items that have to be addressed makes clear the need for a comprehensive set of checklists. They have proven to be an extraordinarily valuable part of the process at Intrinsix.

If your next project could benefit from detailed checklists at each phase of the semiconductor development process, especially if you were impacted by a missed item on one of your previous projects, and you could use a helping hand, consider downloading the eBook titled "Five Criteria for Evaluation of Semiconductor Design Service Providers" as an aid in your process or reach out to Intrinsix for a discussion

Five Criteria For Evaluation of a Semiconductor

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Five Criteria For Evaluation of a Semiconductor

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