The Impending Heterogeneous Revolution
This series of blogs looks at the future of the semiconductor industry and the current issues with cost and the resulting stagnation of innovation. The number of new custom ASICs is shrinking and FPGAs do not totally fill the void when it comes to high performance, power, and RF/analog capability. Heterogeneous Systems on Chip (HSoC) composed of individual chiplets, fabricated in their optimal processes and connected on a silicon substrate using heterogeneous 2.5D technology, is the future and the technology and business frameworks are evolving to make this paradigm a reality.
This edition of the blog adds some detail as to why custom ASICs are so expensive to build. I look at a few rough categories of expenses. In future blogs, I will be discussing some solutions to these high costs. Heterogeneous integration can play a large role in reducing these costs.
The Semiconductor Access Issue (Part 2)
In my previous blog, I introduced the semiconductor access issue and talked about how the rising costs of making new silicon have edged out many of those who wish to construct a custom ASIC. In this blog, I will further break down where the costs of ASIC design lie by examining a fictitious example.
Cost of Hypothetical Design
If we look at a more modest chip development, say an ASIC for a defense application in perhaps 28nm technology. Such a design may have a multicore processor, RAM, ROM, an ethernet/WiFi connection, a machine learning co-processor, and some other interfaces such as USB, DDR, etc. An estimated cost for such a design in such a process is about $50M. The main NRE costs for such a design can be broken out into a few large buckets for illustrative purposes; physical/plant costs, design and verification costs, EDA tool costs, IP license costs, mask costs.
These costs cover all things not related to the design of the chip. They encompass building costs, computers and infrastructure, personnel overhead (IT, HR, Marketing, etc.) and fall into the category of the costs of doing business. They are necessary for any business endeavor and much of it can be accounted for as capital expenditures rather than expenses.
Chip development Electronic Design Automation tools (EDA) are varied and expensive. There are tools for digital design and simulation, analog design and simulation, digital synthesis, clock tree insertion, Power/ground IR analysis, place and route, scan insertion, parasitic extraction, static timing analysis, More??
Even for a large semiconductor companies who are large consumers of EDA tools and who receive significant volume discounts, EDA tools can be a significant expense. For small companies these tools can be a significant barrier to operation. A tool suite for a development team making a fairly complex ASIC might cost between $1M and $5M annually.
SoC designs are typically a mix of home-grown semiconductor IP and licensed IP. There are many reasons to license IP forming the classic “Build vs. Buy” quandary. Suffice it is to say that a team cannot reinvent the wheel for all parts of a design and buying existing, proven IP -especially when that IP implements a common standard- is a sound practice. However, IP costs for many of the common complicated blocks, especially ones where there is significant mixed signal content have grown as has the use (in some cases a necessity) to the point that even for a process node a few generations off of the cutting edge might cost 30% of a mildly complex SoC or $10M - $20M. This IP ranges from the foundation level IP like memory, Flash, and processor cores to more specific IP like high speed SERDES, USB, DDR controllers. Much licensed IP also comes with per unit royalty payments as well. Figure 1 shows the increased use of external IP as process nodes have advanced.
Figure 1. Costs of IP vs. Process Node
In order to actually fabricate a chip, the final layout database created by the designers, known as the GDSII (Graphics Data System 2) is sent to a mask production facility (This is tapeout – It used to be sent on tapes!) for the creation of physical masks. These masks are large glass plates which are patterned in such a way as to create the transistors and circuits of the desired chip. The masks are like negatives in a photographic process except rather than a single mask, each process needs multiple masks to form a complete design. The number is determined by the number of layers and process complexity. For example, the geometries of the most advanced processes are already on an atomic scale. A 7nm transistor channel in silicon is about 35 atoms wide. In order to manufacture at these very fine geometries, new lithographic techniques including pitch splitting, spacer patterning, and EUV lithography are being used. These techniques require extra processing steps to be made reliable and many more masks to be made. Due to the large number and added complexity of these masks, the cost of initial mask manufacture has risen into the tens of millions of dollars. Figure 2 shows how the number of process steps needed increases dramatically after 20nm. While each of these steps do not require a mask, the number of masks required also rises dramatically. Additionally, the number of design rule checks needed to create the masks also undergoes an exponential increase as new problems and physical interactions are encountered as the feature sizes shrink.
Figure 2. Number of Process Steps vs. Node
Perhaps the worst part is that after the masks are created, there is no guarantee that the chip created will work. Design errors not caught by verification of system requirements unforeseen might cause a re-spin of some or all of the masks. The huge mask expense furthers the need to do thorough vefification.
The design costs are still the largest area of spend in a new semiconductor development program as it should be accounting for maybe 60% of the total. For the most part, the money goes to paying salaries of large teams. The design is fun part everyone wants to do and what everyone thinks of when they think of chip development costs. However, the actual RTL design is typically 5-10% of work. Of the design phase, design typically accounts for 20% - 30% of the work and verification 70% - 80%. In order to have a reliable product, massive amounts of testing (called verification in the pre-tapeout phase) must be performed. Simulation test benches must be created, and test coverage of block level interactions must rise to sufficient levels. Furthermore, when anything is changed, often the verification must start over to make sure something wasn’t broken while fixing something else. The process of verification is both painstaking and crucial. Testbenches must be designed along with Bus Functional Models (BFMs) to stimulate the individual blocks as well as the overall design. Designs are typically so complex that every possible combination of bits cannot be tested. EDA tools which create randomized tests are helpful in this situation.
Then there are all the important but less sexy things people don’t want to talk about such as test and test hardware development, documentation, software driver development, validation and application board development, back end logistics. These tasks, while not technically in the chip level design cycle are crucial to making a manufacturable and sellable product and the costs can add up quickly.
Fate of Most ASICs
To the point in the project before design has started, nothing has been done, yet between tools, licensed IP and masks, maybe $25M has been spent. It is at this point in the analysis that everything stops, and most custom ASICs don’t get built. For large manufacturers in high volume consumer markets such costs can be amortized over tens or hundreds of millions of units sold and the economics of even ultra-fine line geometries might make sense. However, in military, defense, and scientific markets where volumes are low the cost of custom ASICs quickly becomes prohibitive. This is true for small startup companies looking to innovate on the hardware side and the semiconductor industry as a whole. The up-front NRE cost barriers are such that they stifle large numbers of players from competing – even at process nodes over 10 years old. The result is either nothing gets built or a design is shifted to an FPGA where the power and performance can be a factor of 1000x worse.
In this blog, I’ve talked about the barriers facing SoC development and how costs have risen to the point that many new custom designs are no longer being built. Some of these barriers are; tool costs, IP costs, design costs, and mask costs. In future blogs I will address how the industry is evolving and some possible solutions to these current problems.