The Impending HSoC Revolution - Potential Solutions to the ASIC Cost Barriers
- SoC Design, Semiconductor IP, ASIC Design
- May 30, 2019 7:35:00 AM
This series of blogs looks at the future of the semiconductor industry and the current issues with cost and the resulting stagnation of innovation. The number of new custom ASICs is shrinking and FPGAs do not totally fill the void when it comes to high performance, power, and RF/analog capability. Heterogeneous Systems on Chip (HSoC) composed of individual chiplets, fabricated in their optimal processes and connected on a silicon substrate using heterogeneous 2.5D technology, is the future and the technology and business frameworks are evolving to make this paradigm a reality.
The previous blog discussed a few main categories of costs that limit the creation of custom ASICs. This blog will touch on some evolving solutions to these problems.
Potential Solutions to the ASIC Cost Barriers
In the previous blog, I created a very simple cost model for the creation of a mid-level custom ASIC and showed how the costs quickly became prohibitive for most low volume ASIC applications, creating a serious problem for defense and scientific applications. The cost buckets I described are: EDA tool costs, IP costs, design costs, and mask costs. There are really two aspects to these costs; total expenditure and liquidity. The total expenditure is straightforward, things are just too expensive. However, from a practical point of view, it is often the liquidity issue that stalls projects. Essentially, there must be a large up-front outlay of capital to get ASICs made, well out in front of any realized revenue. Further, with the risk of a chip re-spin, unforeseen design complications, and/or the market disappearing it becomes a hard decision to move forward with a design. In this blog, I will look at some potential solutions.
Electronic Design Automation (EDA) Tool Costs
EDA tools such as those offered by the three major tool vendors (Cadence, Synopsys, and Mentor) are an absolute necessity for anyone looking to design a chip. There are many different software tools needed which aid in the design, simulation, verification, layout, and manufacturability of the silicon chip. Large semiconductor companies typically get large volume discounts that enable them to have access to full suites of tools at the best prices. The costs to small design houses for the tools alone can often be prohibitive and the money is due up front, well before any product is available. A tool suite can cost several million dollars per year to design a modern semiconductor device.
One obvious solution to the high EDA tool costs is the development of free open source EDA tools. There are a number of good free development tools available such as Verilator for digital design and simulation and Xyce for analog design and simulation, but free full suites of tools that can be used to take a design from concept to mask do not exist yet. An issue with open source tools is that they tend to lag the development of new tools for new processes. Developing tools for the most cutting-edge processes is a huge effort requiring close interaction with foundries. Such interaction/access is only available to the trusted foundry partners who have NDA and other legal agreements. Foundries are not keen to expose the fine details of their new processes to the entire open source community. Effective tools and PDKs are the result of a number of test wafers and model refinements. Another issue with open source tools is the lack of support that a design team can leverage when problems arise.
Modern designs are too large and complicated for any company to design an entire ASIC from scratch. To keep from re-inventing the wheel for every SoC, many blocks – especially those that are based upon industry standards – are often sourced from an outside IP vendor. The vendor often has realized the IP in practice and has a test report and verification vectors. The vendor can also provide integration support and manages their IP to keep it up to date. However, the cost of acquiring this third-party IP, especially for some critical leading edge and differentiating functions such as SERDES, can prove costly to the point of being prohibitive. Each major IP block can cost millions to license and there often can be a per-unit royalty charge as well.
One solution to this problem is to use free open source IP. For years, the open source software community has enabled many developers with free code implementing a variety of protocols and applications and the hardware community is now following suit. New repositories of open source hardware IP are popping up and providing various levels of quality of digital IP in the form of Register Transfer Language (RTL). On such sites as OpenCores, Github, and LibreCores as well as at many university websites one can find IP for many common blocks and standard interfaces. However, at this point there is no good way to search across the universe of sites and/or determine the relative quality of the IP from people who have used it before. The other issue is that analog and memory blocks are highly process dependent and are hard to share both from the technical and business/logistical point of view. One major piece of often licensed IP is the processing core. The RISC-V consortium now has a free open source ISA with RTL and tool generators. This is a significant advancement in the industry and I will be blogging about in the future.
A major problem with free open source IP, however, is that the quality is often unknown and the integration into a system can be involved. Full verification (which accounts for most of the design time) is always needed. If a problem arises, documentation is scarce and there are few to any people to rely on for support. Often, the designers need to dig in and become experts in the thing that was meant to be a black box.
Design costs cover the actual engineers who develop and test the product. Often, for accounting reasons, many other expenses such as facilities, overhead, support, etc. are rolled into an engineer’s salary and benefits to form a Loaded Labor Rate (LLR) which is the effective hourly rate a company pays its employees all inclusive. These costs cannot be avoided, since this is the main product development task and is often the largest cost in developing an ASIC. One common trend over the past two decades has been to outsource employees to countries such as China and India where the LLR is significantly less expensive. While this has been effective in some cases, there are a myriad of issues. For example, the cost of setting up remote design centers has skyrocketed as employees in these countries have begun to earn more. Retention of key employees in these countries also tends to be a challenge and momentum on large projects is often lost. There are also issues with protection of intellectual property in these countries as well as management issues due to large differences in time zone and language. For military ASICs, going offshore is often not an option. The solution is to keep design teams as small as possible, minimize complexity, use open source IP, and to re-use as much as possible.
After a design is complete, the semiconductor mask set must be produced. In a modern flow, the GDSII database is sent to a mask design house which fabricates a bunch of glass plates each uniquely patterned to correspond to a step in the wafer development process. Unfortunately, the cost of having these masks produced has risen sharply as processes have become more complex requiring dramatically more masks. As shown in Figure 1, mask costs are easily in the single digit millions of dollars for some of the less advanced nodes and they are in the tens of millions for the cutting-edge nodes.
Figure 1. Approximate Mask Costs vs. Process
When a physical thing needs to be delivered, someone needs to pay something. This is what sets the hardware industry apart from the software industry. Afterward, wafers need to be purchased and tested as part of the ongoing COGS (Cost of Goods Sold), but the masks are NRE.
One way to avoid mask costs is for the industry to move to maskless lithography. Rather than constructing physical masks, which are analogous to developed film negatives in a photographic process, an electronically controlled lithography system is used. These approaches tend to be slow and lack the resolution needed for the most advanced processes. The slow speed limits their use to low volume applications. However, the ability to quickly change the data file and avoid the need to pay for a new physical mask is a major upside.
Maskless lithography was a major area of research focus for DARPA up until around 2005 when it started to defund the initiatives. While this approach is very promising, there are still some business-related issues that need to be worked out for maskless lithography to become a viable option for the masses. Currently, the foundries do not make the masks, they are made by third parties. For a maskless lithography process to become viable, the maskless machines need to be brought into the foundry. The foundries need a financial incentive to bring low volume production machinery in house and a means to recoup the costs of these very expensive machines. Amortization of these costs would need to follow a model of an up front “mask” cost and then a premium on subsequent wafers. If the upfront charge is too great, the advantage over the current system is lost.
Is It Enough or Is there Something Else?
So far, I have outlined approaches that could save a developer of ASICs a substantial amount of upfront NRE. If an entire free open source EDA tool chain existed, AND if free open source IP existed, AND if a pay as you go maskless lithography approach existed, only about half of the $50M development cost will be saved. Still, the designers are left with a pretty hefty price for a low volume ASIC. Where does the money go? There is still the design cost element. Again, within the design realm, 70% - 80% of the time and cost is due to IP integration and verification. Thus, even if the IP is “free” there is still significant cost to bring it in, connect it to a design, and verify it all works. Verification always needs to be performed even when IP is known to work, or Murphy’s Law will come into play. Even with the aforementioned cost-saving approaches, the sheer complexity of modern designs requires either a large sum of money or a new approach to ASIC construction.
While design re-use through IP integration has been a key component to the rapid advancement of the semiconductor industry over the last 40 years, the IP acquisition, re-integration, and re-verification costs is what currently holds it back. We are no longer re-inventing the wheel, rather we are just re-testing it. What is really needed is a way to re-use IP at the physical level and avoid the acquisition and testing penalties. The true solution is through the use of chiplets. Chiplets are small die with standard interfaces which implement specific functions (IP) that can be recomposed into larger systems. Effectively, chiplets are physical manifestations of IP. The main differences between existing off-the-shelf chips of today and chiplets is the level of complexity, specificity, and interface. A chiplet has more specificity and less overhead and is not meant to stand alone but rather is meant to be combined with other chiplets to form a system. This runs counter to the SoC mentality of monolithic integration that has driven the industry for so long.
Figure 2. Benefits of NRE Reduction Strategies
In this blog, I’ve talked about some of the potential solutions to the high costs of making an ASIC. These included open source EDA tools, open source IP, outsourcing, and maskless lithography. While these approaches have the potential to save significant amounts of money, I conclude that design re-use through chiplets is the true way forward. In future blogs I will look further into chiplets and how heterogeneous construction using 2.5D integration (building HSoC’s) provides a path forward for the industry as a whole.
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