This series of blogs looks at the future of the semiconductor industry and the current issues with cost and the resulting stagnation of innovation. The number of new custom ASICs is shrinking and FPGAs do not totally fill the void when it comes to high performance, power, and RF/analog capability. Heterogeneous Systems on Chip (HSoC) composed of individual chiplets, fabricated in their optimal processes and connected on a silicon substrate using heterogeneous 2.5D technology, is the future and the technology and business frameworks are evolving to make this paradigm a reality.
This first blog introduces the access issue that motivates the need to start to build semiconductors in a different way. The race toward monolithic integration has been fruitful to this point but has now led us to a point of unaffordability.
The Semiconductor Access Issue (Part 1)
As process technology moves to smaller nodes the cost of chip development is growing exponentially more expensive. Whereas some very high-volume applications can afford to continue down this path, many custom ASIC and low volume designs are no longer tenable leading to a substantial reduction of new ASIC designs and a significant problem for the military and scientific communities. The inability of the semiconductor industry to continue along the trajectory predicted by Moore’s law -at least on an affordable path - has led to an access problem for the vast majority of the industry. This is particularly true for consumers and providers of custom ASICs.
Computational Efficiency
Application specific integrated circuits (ASICs) are power and speed optimized systems designed to perform specialized functions. Often, an off-the-shelf CPU-based SoC using custom software either cannot perform the task or requires too much power to do so. Applications such as Military/Defense, cloud processing, scientific/engineering computing, machine learning, smart sensors, servers, and smartphones all use custom ASICs. One common fallback used by those who cannot afford a custom ASIC is to use a Field Programmable Gate Array (FPGA). Such devices use a pre-defined regular structure that can be configured with a logic design much the same way a processor can be programmed. This solution is flexible and powerful in that it allows rapid prototyping and fast fabrication. The device once purchased and placed on a board can be programmed and reprogrammed in a matter of minutes. However, the FPGA suffers from a variety of limitations including; high silicon area, lower speeds than a custom silicon design, higher power than a custom design, and lack of analog integration.
Computational efficiency measured in the number of operations per second per watt of energy has continued to increase as semiconductor technology has advanced. This is an important figure of merit both for military systems where power sources may be limited or in wearable or remote sensing applications. Figure 1 shows a historical perspective of the improvements in semiconductor computational efficiency. As can be seen, while the process nodes have gone to smaller linewidths, computational efficiency in any given class of IC has improved by roughly a factor of 10. However, the computational efficiency improvement that can be achieved for a given task by a custom ASIC over a general-purpose processor is roughly two to three orders of magnitude.
Figure 1. Computational Efficiency (DARPA)
Figure 1 also shows that FPGAs are not the complete solution. While FPGAs do allow for the construction of custom logic and can significantly outperform general purpose processors, their extra area, higher routing resources, and logic regularity leads to significantly less computational efficiency than a custom IC design.
Another benefit of custom ASICs is the integration of analog, RF, memory, and other specialized functions not often found in general purpose off-the-shelf. These functions may not be available on the general market or their inclusion may be power and/or space prohibitive.
NRE Cost Explosion
As process technology has advanced, the semiconductor industry has been able to keep on track with the Moore’s law prediction for over 40 years. This prediction that the number of transistors on integrated circuit chips will double every 2 years was largely fulfilled by corresponding shrinking of process linewidth while voltage scaling has kept power dissipation to a manageable level. However, current process technology is reaching physical limits that make further shrinking exponentially more difficult resulting in a huge increase in the development cost of cutting edge SoCs
The rapid cost increase in Non-Recurring Engineering (NRE) expenses has begun to lock out all but a handful of major semiconductor manufacturers and it has created major limitations for DoD, systems houses, and startups. As such, there is an accelerating issue of access to high performance/low power technology for the vast majority of the industry – all of which is stifling innovation and progress. It also must be noted that many custom SoCs which perform specialized functions do not have large volumes over which to amortize the large development costs making the unit costs prohibitive. Figure 2 charts the rising NRE costs vs. the processing node.
Figure 2. Cost of Chips vs. Processing Node (DARPA)
It can be seen that there is an exponential rise in costs to stay on the cutting edge. As can be seen, even mid-range silicon developments can cost $50 - $100M and take 3+ years.
There are a number of major factors for this. First, it must be stated that more advanced nodes are newer, and costs will always be higher for the newest most advanced thing. Just compare prices of this year’s model of your favorite car as compared to what you can get last year’s for. Newness factor aside, there are some major drivers of cost. First, as the industry has pushed up against the physical limits of materials, the cost of processing and masks has skyrocketed. Another reason for the skyrocketing cost is the sheer complexity of the new designs. As the shrinking processes have allowed for more circuitry to be put on a chip, designers have filled that space. However, the costs of managing expanding design teams and performing verification on such large scales has ballooned development budgets. However, as mentioned before, these are the costs of doing business at the cutting edge and ultra-high volume applications such as cell phones can bear these costs.
What’s Next
In this blog, I introduced the access problem facing the semiconductor industry. In my next blog, I’ll take a deeper look at where some of these costs lie.
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