The DARPA CHIPS Program
- SoC Design, Semiconductor IP, ASIC Design
- Jul 31, 2019 7:33:00 AM
This series of blogs looks at the future of the semiconductor industry and the current issues with cost and the resulting stagnation of innovation. The number of new custom ASICs is shrinking and FPGAs do not totally fill the void when it comes to high performance, power, and RF/analog capability. Heterogeneous Systems on Chip (HSoC) composed of individual chiplets, fabricated in their optimal processes and connected on a silicon substrate using heterogeneous 2.5D technology, is the future and the technology and business frameworks are evolving to make this paradigm a reality.
This edition of the blog will discuss the DARPA Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program. This initiative has a vision of a modular infrastructure of discrete chiplets from which HSoCs can be inexpensively and reliably manufactured. The program aims to explore the technological barriers from design to integration to tools to make this vision a reality.
The DARPA CHIPS Program
Recognizing the issue of the skyrocketing costs and the resulting decreased access to advanced nodes in the semiconductor industry, DARPA started the Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program in 2017 to help lower the design costs associated with advanced SoC’s. The CHIPS program expects to spend ~$70M and is part of DARPA’s Electronics Resurgence Initiative (ERI) which itself is a 5 year $1.5B program to address the challenges seen by Moore’s law. CHIPS is developing design tools, integration standards, and IP blocks required to demonstrate modular electronic systems that can leverage the best of DoD and commercial designs and technology.
The vision of the CHIPS program can be seen visually in Figure 1. Here, rather than implementing all functions on a single monolithic piece of silicon, a modular approach is taken where each major function is manufactured separately in a process well suited for that function. Silicon systems are then built up from these chiplets.
The innovation is the technology used to connect these chiplets. Rather than using a printed circuit board as is done today for many products, CHIPS aims to use a silicon interposer to connect the chiplets resulting in a much finer pitch set of interconnections. The silicon interposer can be designed using the same feature sizes as those used on a silicon IC allowing for a far denser set of interconnects, closer chip to chip spacing, and ultimately faster speed, less power, and a smaller form factor than a printed circuit board (PCB) or hybrid built up from discrete components.
Figure 1. CHIPS Vision (DARPA)
An often-used semiconductor efficiency figure of merit, SWaP (Size, Wattage, and Performance) is defined as:
This metric is similar to another often-used military metric where SWaP stands for Size, Weight, and Power. Either way, the CHIPS program seeks to improve SWaP of discrete designs by driving performance, power and space to near monolithic levels while at the same time increasing re-use and modularity thus reducing cost, risk, complexity, and time to market. Figure 2 shows the goals for the CHIPS program. It has been recognized that one of the key enablers of any heterogeneous system design is the standardization on high bandwidth, highly power efficient, physical interfaces which would enable complex functions to be split across chip boundaries. A power efficiency benchmark of < 1pJ/bit/transition has been determined to be the critical interface target whereby heterogeneous systems pay only a modest penalty for interface power vs. monolithic designs.
Figure 2. Chips Program Metrics (DARPA)
In phase 2 of the program, application level designs will be attempted where systems will be built up from chiplets and interposers. Finally, in phase 3 an analysis of the benefits and tradeoffs of heterogeneous design along with the applicability to military systems will be made.
The CHIPS program includes the following announced performers:
These entities are working together in phase 1 to develop chiplets, evaluate interfaces, investigate chiplet-to-interposer bonding technologies, and work through the issues needed to produce chiplet based systems in an open ecosystem environment. The current design projects being worked on include, a 60GHz ADC/DAC sampling chiplet, a security chiplet, a memory interface chiplet, a Neural Network chiplet, and a power supply chiplet. Additionally, bonding technology to silicon and glass interposers as well as a move from the current 55um pillars to 10 um pillars is being investigated.
A key issue in developing a new heterogeneous infrastructure is the agreement of a common interface with which to communicate over. There are a number of choices, some of which will be discussed in a future blog, but the DARPA CHIPS program has settled on Intel’s Advanced Interface Bus (AIB). This highly efficient parallel bus was developed by Intel for their Stratix FPGA devices so that chiplets could be added to that platform and was subsequently made open source. This is now an Apache license royalty free piece of IP that the heterogeneous community can use to create chiplets. The design files can be found on GitHub at: https://github.com/intel/aib-phy-hardware Having access to a free state-of-the-art interface with a major semiconductor company and DARPA driving the standard is a real boost to the chiplet community and may be a major enabler for this technology.
In this blog, I’ve talked about the DARPA CHIPS program. This program looks to further heterogeneous technology to ease the NRE burden for both military and commercial developers. Strategic technology such as the creation of chiplets, the adoption of a common interface, the investigation of chiplet to interface bonding, and the development of a design methodology are being investigated.
In future blogs I will address chiplet interface schemes and take a closer look at the AIB bus.
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