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Process Scaling Has Not Been Kind to Analog Circuits

Everyone is familiar with Moore's law, and the extraordinary impact that it has had on integrated circuit technology. For decades, it accurately predicted the rate at which feature sizes could shrink by process scaling – and the resulting increases in density, performance, and functionality of integrated circuits over time. There can be no doubt that the process scaling described by Moore's law has been a driving force in technological change over the last forty years, and has contributed significantly to the world economy (see the figure below).

Moores Law versus Semiconductor  Shipments

However, process scaling has not been kind to the analog circuits in mixed-signal ICs. This is because the innovations that enable scaling have typically focused on digital circuitry, leaving the analog circuitry compromised due to:

  • Various non-ideal effects that arise which limit the analog characteristics of a MOSFET, as well as its useable dimensions and operating points, and
  • Increased variability among neighboring devices on the same (and, even on different) die as a result of the physically smaller dimensions of a new process node.

These effects create problems that have to be confronted before an IC can be fabricated. This is absolutely essential for first pass success. Failure to do so will, at best, lead to unpredictable behavior, and lower yields; and, at worse, will result in operational failure, and costly rework.

We employ several strategies at Intrinsix to address these issues.

First, and foremost, we have experts on staff that specialize in analog and mixed-signal designs, who understand the degrading effects of process scaling, and, most importantly, know the latest best-practice techniques for dealing with the non-ideal effects and the process variation caused by scaling. These engineers know what to look for when evaluating the analog performance of a new process, and they stay abreast of the latest techniques that can be used to manage any additional limitations.

To deal with the adverse effects of scaling, it is important to understand what they are. For example, in a bulk CMOS process, an analog designer would be concerned with things such as:

  • the short-channel effect,
  • the reverse short-channel effect,
  • the shallow trench isolation (STI) stress effect,
  • the well proximity effect,
  • random dopant fluctuation,
  • gate leakage,
  • intrinsic gain degradation, and
  • lower voltage headroom.

The first step toward understanding the effects that scaling is likely to have on a new IC design is to perform characterization simulations on single transistors. This allows us to explore the issues, and look for troublesome device sizes and operating points. In addition, they can provide insights that lead to better area/performance trade-offs. Ultimately, they give us the basis of a plan to address the analog portion of the design.

Once we understand the problem areas, it's necessary to draw upon the available techniques and best practices for addressing the negative effects of scaling. These fall into two broad categories – circuit-level techniques employed at design-time, and layout techniques used during physical design.  These methods are typically oriented toward reducing the effects of variation. Many of them are designed to compensate for mismatched circuit elements, either by augmenting the circuit design so that it is more tolerant of mismatched elements or by laying out the individual transistors in the circuit using specialized techniques that promote better matching. The techniques that work best will depend on the process technology, the type of analog circuitry used, and the requirements of the design. Together, these will define the trade-offs that can be made (e.g., area vs. performance) to best implement the analog circuitry.

Finally, it's useful to note that simulation results may look promising, even if strategies are not employed to minimize the influence of the aforementioned effects. It's easy to be lulled into a sense of complacency. This is why it's so important to have experts involved. Without them, it's easy to overlook potential problem areas.

In summary, it's critical for first spin success to address the effects of scaling on analog circuits. This requires experts to stay abreast of the effects of scaling, and the latest techniques and best practices for mitigating the deleterious effects. Intrinsix recognizes this and has been successfully implementing mixed-signal designs for years.

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