SDM Data Converter Architecture Considerations for Custom IC Designs

SoC Design, Mixed Signal Design, ASIC Design
Mar 26, 2018 8:31:00 AM

Sigma delta modulators (SDMs) are widely used as data converters in mixed signal integrated circuits, especially in applications that require sensing of real world signals such as temperature, audio, and pressure sensors, image acquisition, accelerometers, and radio receivers. They are cost effective, inherently insensitive to process variations, and highly precise for applications with narrow passbands. But despite their wide suitability, they can present serious challenges for IC designers working in environments with tight power and area requirements.

Essentially, an SDM (also referred to as a DSM) is an oversampled data converter, which transforms analog signals into a digital data stream. Oversampling (i.e. at a frequency higher than the Nyquist rate), in conjunction with filtering and noise shaping techniques results in higher effective resolution and lower power consumption than can be achieved with other ADC architectures. Furthermore, properly designed SDMs are stable across process variations and operating conditions, making them ideally suited for ASIC and SOC designs.

There are four commonly used architectures for SDMs, broadly organized into feedforward and feedback topologies. They are:

Cascade of Integrators, Feed Forward (CIFF)
Cascade of Integrators, Feedback (CIFB)
Cascade of Resonators, Feed Forward (CRFF)
Cascade of Resonators, Feedback (CRFB)

Example diagrams of CIFB and CIFF architectures are shown here:

(Matlab Simulink models of SDMs designed at Intrinsix Corp)

Illustration 1: Example of third order CIFB architecture

Illustration 2: Example of third order CIFF architecture

The performance of an SDM can be characterized by it's Noise Transfer Function (NTF). All of these architectures are capable of implementing the same NTF. So why would you choose one over another?

The answer lies in the other application specific trade-offs, including power consumption, capacitor area, signal transfer function (STF), and maximum sample frequency. The goal is to choose an ideal STF in the passband, leading to maximum stability over the widest operating range. But system requirements can work against an optimal signal transfer function; for example, die area is often a dominating limitation. To reduce size, designers may be forced to use smaller capacitance values, leading to a less than ideal signal transfer function.

The question then becomes: which of these architectures is the best choice for your system? Do you choose the one with the best STF, or one that better meets other system specifications and constraints, even though the STF is not ideal?

We confront these kinds of trade-offs frequently at Intrinsix. Our philosophy is to do a thorough analysis up-front, before engaging in detailed silicon design. A methodical analysis during the design phase can save expensive and time consuming rework later on.

In practice, this means evaluating the NTF and STF magnitude plots for each SDM architecture during the design phase. The objective is to achieve a flat STF in the passband. But as we've seen, this can be difficult, given the size constraints on the capacitors. Each architecture will offer it's own set of trade-offs. The task is to thoroughly explore these trade-offs to end up with an implementation that works reliably in the system.

To illustrate this point, consider the STF and NTF plots of a 3rd order CIFB and CIFF examples shown in illustrations 1 and 2.

Illustration 3: NTF and STF plot of 3rd Order CIFB

Illustration 3 shows the magnitude response of unquantized NTF and STF of a 3rd order CIFB SDM. The NTF and STF plots shown in blue and red respectively are ideal, especially the STF that is flat in the passband. Unfortunately, the capacitor sizes for the CIFB implementation push beyond the die size limitations.

Keeping all SDM parameters the same (oversampling ratio, order, etc), but changing the architecture to a feed forward type (CIFF) we get a different performance for the STF as shown in illustration 4.

Illustration 4: NTF and STF plot of a 3rd order CIFF

The STF for the CIFF is not flat in the passband and hence not ideal. This tells us that the SDM might be unstable for certain operating conditions. But it has smaller capacitance values, and thus reduced die area. If this design can be shown to be stable over the operating range required by the system specifications, then it will suitable choice for the system.

This type of analysis required to evaluate these trade-offs can be time consuming, even if the engineers performing the analysis are highly experienced. Intrinsix has developed a proprietary tool suite based on several patented technologies to help automate this analysis. The tool suite is called the Intrinsix Sigma-Delta Refinery which, when deployed by the Intrinsix Mixed Signal Design Team, allows the creation of finely tuned, highly optimized SDMs. The Refinery allows us to quickly converge on optimized SDM implementations is much less time that is typically possible with a manual design methodology.

Using automated flows within the Sigma-Delta Refinery, we can rapidly perform the necessary simulation and analysis to validate the stability of the SDM in the passband. Though the STF may not be ideal, the design might still meet the performance requirements of the system.

By analyzing each of the four topologies in this manner, it will be possible to find the architecture that best meets stability, area, power, and signal transfer function trade-offs. The best choice is not always the design with the ideal STF and NTF curves. But the key is to perform this analysis prior to silicon design. Identifying and resolving system integration issues prior to system implementation, and prior to tapeout, will reduce the risk of unanticipated, expensive rework.