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Chiplet Interfaces

This series of blogs looks at the future of the semiconductor industry and the current issues with cost and the resulting stagnation of innovation.  The number of new custom ASICs is shrinking and FPGAs do not totally fill the void when it comes to high performance, power, and RF/analog capability.  Heterogeneous Systems on Chip (HSoC) composed of individual chiplets, fabricated in their optimal processes and connected on a silicon substrate using heterogeneous 2.5D technology, is the future and the technology and business  frameworks are evolving to make this paradigm a reality.

This edition of the blog will discuss different interfaces that are being proposed for use for chiplet interconnection and HSoC construction.  We’ll focus on Intel’s Advanced Interface Bus (AIB) as it provides a number of advantages and takes full advantage of silicon interposers and heterogeneous 2.5D technology.

Chiplet Interfaces

Once a collection of chiplets have been selected from which to build an HSoC , the problem of how to interconnect them arises.  Unfortunately, there is no universally accepted standard for chiplet interconnection.  This is true from the physical layer on up.  Lack of universal standards is a major impediment to the widespread acceptance of heterogeneous SoC design.  The physical layer consists of two portions, the actual physical medium comprising the interposer and bumping connections and the logical definition of the interface.  For this blog we will assume that the physical medium is a passive silicon interposer connected with copper pillars (who’s current production level bump spacing is ~55um) and focus more on the interface definition.

Interface Approaches

There are three main approaches to date, Legacy/SerDes, ultra-short reach (USR) serial, and bunch of wires (BOW) interfaces.  While the legacy approaches have the distinct advantage that there are many die available today with these interfaces, the optimal power and architectural partition may not be reached as these interfaces were designed to drive board level loads and distances and burn far more power than would be necessary in an on-chip heterogeneous environment.  Furthermore, these interfaces place an upper bound on bandwidth and latency, limiting the partitioning advantages that can be achieved in heterogeneous design. 

USR approaches serialize the data (often using several bonded serial channels) and form a short reach communication system.  While they can achieve fairly good power consumption and fairly compact size, they can be complicated to design, integrate, and transfer between processes.  They also incur a heavy latency penalty due to the serialization process.  There are a number of competing USR busses with different bandwidth/power tradeoffs and it is unclear which one will prevail. 

The third common approach is to use a highly parallel approach, connecting wires in a similar manner as would be done on chip.  A leading interface, Intel’s AIB bus is a channelized parallel bus (BOW approach) which achieves excellent bandwidth and power numbers.  It does, however, require a footprint with many micro-bumps and modest design effort to interconnect chiplets.  Such wide busses necessarily require the use of a silicon interposer where the other approaches can be used with organic substrates.  


It can be reasoned that the true difference between a chip and a chiplet is that a chiplet is specifically designed to be put in an HSoC and thus takes advantage of the prodigious numbers of  very short interconnect wires available.  As these connections are a natural consequence of using a silicon interposer, their incremental cost is near zero.  Thus, to maximize the efficiency of the interposer, very wide busses should be used.  When the cost of a wire is negligible, as many as possible should be used and the driver/encoder on each end should be made as simple as possible.  Furthermore, in the HSoC environment, the wires are necessarily short which reduces clock skew and allows for increased parallelism.  The design of a chiplet should anticipate the use of the advanced packaging and be architected in the same way as would be done in a monolithic setting to reduce power and latency.  Complex encoding and multiplexing schemes, typically as used when limited communication paths are available, should be avoided.

While we believe true heterogeneous integration only exists on silicon interposers and believe the AIB bus is the solution to most high speed chiplet to chiplet problems, we are also practical and take the stance that one should use the best interface available to fabricate an HSoC.   This might mean connecting a processor chiplet and memory chiplet with an HBM interface (the correct interface for this job) and use an available SPI port to an audio codec, and an AIB port between the processor chiplet and GPU chiplet.  Since in the beginning all chiplets will not all have compatible interfaces, the practical approach is to stitch together the chiplets using the interfaces available.  While this may not lead to an optimal power dissipation profile, significant power will still be saved by reducing the I/O drive strength of the I/O devices and limiting the physical parasitics to a minimum.

The Advanced Interface Bus (AIB)

The development of a common interface is a difficult task as there are many factors to consider and not all applications necessarily weigh the pros and cons in the same way.  Some factors to consider in an interface technology are cost, area, energy per bit, bandwidth, latency, distance, scalability, and the ability to realize in different process nodes.  Fortunately, with the backing of DARPA, Intel has made its high-performance Advanced Interface Bus (AIB) for use in connecting chiplets public and free  through the open source framework of git-hub.  This interface delivers the highest bandwidth and lowest power per bit of any competing solution and achieves near monolithic interconnect performance.  Intel has been producing products with this interface for several years and currently offers it on its Stratix 10 FPGA series to connect chiplets to the FPGA fabric.  With Intel’s presence in the industry and an emerging consortium adopting it, the AIB is positioned to become the chiplet interconnection standard.

AIB Interface

The AIB is a PHY level bus specification developed and used by Intel.  It is a highly parallel master-slave bus consisting of 25 independent channels – 24 data and one control that can be clocked up to 1GHz.  This bus also supports double data rate operation and in its fastest implementation can deliver several Tb/s throughput.   A clock forwarding scheme is used to synchronize the bus.  The AIB is highly customizable in terms of the number of channels and bus width and supports two main flavors, a high performance “Plus” version and a scaled down “Base” version for less demanding operations.  The “Plus” version supports double data rate clocking to achieve a per line throughput of 2Gb/s-per wire.  The AIB has been designed to deliver < 1pJ/bit operation which is considered the threshold for near monolithic power operation.  The AIB spec calls for at least a 10 mm bus length.  There is also a scheme for channel calibration and pin redundancy to improve chiplet to interposer bond yields.  As part of the CHIPs program, Intel has granted license for others to build and use it.   Figure 1 shows a high-level block diagram of two chiplets communicating over an AIB interface.

chiplet-to-chiplet-interfaceFigure 1. Chiplet to Chiplet Interface (Intel)

Guidelines for the physical layout of the AIB are set forth in the AIB specification.  Typically, the channels are laid out as a stacked column as shown in Figure 2 with the bump pattern alternated for maximum density.


Figure 2. AIB Column and Pad Layout

Table 1 shows a quick comparison between using the wide BOW AIB interface vs. using a more traditional high-speed serial interface to connect chiplets.



Finally, it should be noted that the AIB interface is evolving as the HSoC environment evolves.  Intel has recently announced the next generation of AIB which they call , Multi-Die I/O (MDIO).  This interface allows maximum operation up to 5.4GHz and reduced the voltage swing from 0.9V to 0.5V.  The net result of these changes is to increase the total bandwidth and bandwidth density while also improving the power efficiency to 0.5 PJ/bit.

What’s Next

In this blog, I’ve talked about the need for chiplet interface standards and several of the interface standards.  I’ve focused on Intel’s Advanced Interface Bus as it is well suited to the benefits afforded by silicon interposer design and is backed by large companies like Intel and government research organizations like DARPA.

In future blogs I will address the chiplet ecosystem and how it may evolve as well as which chiplets are actually needed to make a viable ecosystem.

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