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Semiconductor Design & Verification Articles

CadenceCONNECT: Mission Critical featuring Intrinsix Corp.

At CadenceCONNECT, Cadence and members of the user community presented optimized design methodologies for mission-critical electronics system applications like A&D, safety, security, 5G, and others.

cadence-connectThe event brought together Cadence technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.

CadenceCONNECT: Mission Critical was Live on October 13, 2020 but all the presentations are now on demand and can be found by registering/logging in HERE.  To see the Intrinsix presentations, see below; no registration or login required, but please contact us if you would like to learn more about these topics or what Intrinsix can do for you.  You can request contact HERE.

  • Manjeera Kota, Intrinsix Principal Design Engineer, discusses Built-in-Self-Repair (BISR) Implementation with the Cadence on-demand PMBIST Flow.  Manjeera has a Doctorate in Electrical and Computer Engineering with over 8 years of ASIC Design experience.  She has expertise in Design-for-Test solutions ranging from insertion, integration, and verification.  Manjeera is proficient with concepts of Scan (OPCG, Compression, At-speed testing), Boundary Scan, Memory BIST/BISR. She has worked on projects right from DFT specifications through ATPG pattern delivery.
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  • Manjeera also presented  Hierarchical Test Insertion Flow Through Multiple Levels of Hierarchy to Enable Pattern Migration in Cadence Modus ATPG. .
Hierarchical-Test-Insertion-Flow-Through-Multiple-Levels-of-Hierarchy-to-Enable-Pattern-Migration-in
  • Nick Hassan, Intrinsix Design Engineer, walks us through a Case Study of Design Validation Within the Cadence Protium Platform.  This presentation provides a case study of the validation of a complex SoC utilizing the Cadence Protium Rapid Prototyping Platform.  With careful planning and up-front decision making, porting of a custom ASIC design to the Protium can be a successful and relatively smooth process.  We will present our first-hand experience and lessons learned with this undertaking.  Nick began his career after graduating from Worcester Polytechnic Institute in 2016, where he earned a B.S. in Electrical and Computer Engineering and Robotics Engineering.  He is continuing his education at WPI, pursuing an ECE master’s degree focused in Computer Engineering.  At Intrinsix, Nick has been responsible for design, verification, and most recently emulation of advanced ASICs and SoCs.  Keith Reeder, Intrinsix Technical Manager/Principal Design Engineer, was the moderator for this presentation.  Keith and Steve Stecyk, Intrinsix Director of Engineering, helped with the development of the presentation.
Design-Validation-Within-Protium-Platform-A-Case-Study

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