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Semiconductor Design & Verification Articles

Peter Militello

Peter Militello

Peter is a Technical Manager at Intrinsix’s Marlborough Design Center. As a verification architect he creates verification and coverage plans, implements and leads teams of engineers building environments based on SystemVerilog/UVM methodologies, and drives verification closure. Along with the experience of many ASIC designs successfully released into production and introducing the latest verification tools and methodologies into the Intrinsix verification flow, he is able to reduce product risk and schedule risk in the ASIC verification process.
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Recent Posts

Why Formal Verification Should Be Part of Your Verification Plan
Why Formal Verification Should Be Part of Your Verification Plan

Designing an ASIC that is free of functional bugs is an important requirement for first spin success. Yet as designs grow...

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