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A Confident ASIC Design Path through Co-Creation

The first blog in this series talked about the competitive benefits to differentiating OEM products in hardware as well as software, followed by a high-level view of our co-creation programs. In this blog I would like to talk a bit more about the way we at CEVA and Intrinsix approach collaboration with OEM and semiconductor, for a confident path to turnkey ASIC design or to wireless subsystem design. To illustrate, imagine the kind of SoC you might want to build for a wireless smart speaker or smart home entertainment system. Core to this system is an audio pipeline supporting voice processing for control commands and wireless connectivity through Wi-Fi and Bluetooth connectivity, where the BT connection could be for remote control or audio streaming. We also include on-chip RF for Bluetooth and WiFi.  An overall block diagram is shown below.

CEVA and Intrinsix ASIC design blog diagram

ASIC design co-creation phase I – planning

Planning starts with a detailed discussion on product requirements. A smart speaker will commonly host multiple microphones, automatic echo cancellation and audio beamforming to zoom on voice commands from across the room. Wireless earbuds may only need one or two microphones and depend on bone conduction to pick up voice commands rather than beamforming. For Bluetooth, do you want just BLE or also dual mode to support older devices or richer audio? For Wi-Fi, backward compatibility takes care of most problems, but you may need to worry about interference between Bluetooth and Wi-Fi at 2.4GHz. We have a co-existence solution for that problem.  Integration of the RF transceivers also requires careful planning.

In considering IP selection, CEVA is a market leader in embedded solutions for wireless, audio, AI and motion sensing solutions , which will address may of IP needs of this application. For other functional and parametric objectives, we discuss design and IP alternatives and tradeoffs. Discussion will cover application control, external interfaces if any, and security for secure boot, provisioning, and over-the-air updates (CEVA also has a embedded security root of trust solution). In this stage we should set objectives for power, performance, and quality of service (bandwidth and latency). If you are supplying your own IP or planning on using commercial IP, we will need to discuss how well they fit with overall goals. All major expectations should be finalized at this stage. Then we will build, review, and agree on a final architecture block diagram and list of requirements.

Our methodology puts high emphasis on verification, to ensure we deliver exactly what you expect, and that it works correctly on first silicon samples. For this reason, we will work with you very closely to develop, review and signoff on a comprehensive requirements specification. This should include use-cases and modes of operation, and software to drive those use cases and modes, together with expected exception behaviors. Requirements must cover parametric behaviors as well as functional.

Once the architecture and requirements are fully defined, we will build a detailed project schedule and cost analysis, incorporating labor, IP, tools and other factors. These we will deliver to you in a comprehensive series of documents, from the verification plan and design specification, through to the DFT and implementation plans in the case of ASIC design. Software considerations will also be discussed. CEVA supplies extensive software solutions for many of its IP, such as wireless protocol stacks, audio stacks, and CNN/DNN stacks for AI products. These will be covered in planning discussions and spelled out in the report, to help you understand how you can integrate your existing software into the target hardware.

The planning process for wireless subsystems, is largely similar to that for SoC planning, except that here clients must also supply SoC constraints on the subsystem (such as available clocks, resets, power controls floorplan constraints, etc.).

Co-creation – beyond the planning stage

The rest of a co-creation project follows a standard ASIC design or subsystem design flow, with significant parallelism between assembly, verification, and implementation. RF and mixed-signal integration require specialized skills.  Throughout, we provide updates and invite discussion on the current state of the design. During RTL development, clients will provide test software for us to run, to demonstrate that critical use-cases are satisfied. If they are running FPGA emulations for their own software development, they will take emulation-ready RTL drops as these become available. For ASIC design, we regularly update clients on progress, from pre-physical design timing closure through post physical design timing closure and full signoff.

Our track record is our guarantee

CEVA and Intrinsix puts verification and a tight project plan first in everything we do. These define our contract to you. We have a track record of delivering designs and subsystems to leading systems and semiconductor companies, on time and on spec for 35 years. A significant percentage of the work we do is with defense, medical and other clients who demand very high reliability in process and product. The processes and expertise we have developed with those clients has become embedded in our culture of “right first time”, as you will see in our verification and project management discipline.

We have designed ASICs from smart speakers to wireless surround sound, from smart power tools to smart surgical instruments, from medical implants to wearable and smart health, and from IoT microcontrollers to biometric fingerprint sensors. Many of these applications are in volume production today. Our DSP-based IP solutions include platforms for 5G baseband processing in mobile, IoT and infrastructure, advanced imaging and computer vision for any camera-enabled device, audio/voice/speech and ultra-low-power always-on/sensing applications for multiple IoT markets. We offer sensor processing technologies with a broad range of sensor fusion software and inertial measurement unit (“IMU”) solutions for hearables, wearables, AR/VR, PC, robotics, remote controls and IoT. In wireless IoT, our platforms for Bluetooth (low energy and dual mode), Wi-Fi 4/5/6 (802.11n/ac/ax), Ultra-wideband (UWB), NB-IoT and GNSS are the most broadly licensed connectivity platforms in the industry.

Our combined expertise in IP and in ASIC design delivery is your assurance that CEVA and Intrinsix is the right choice for your next ground-breaking product.

Contact us to learn how we can help with your co-creation plans.

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