5G / MM Wave IC Design Techniques
High frequency switching circuits are becoming increasingly common in mixed signal ICs, driven by the growth of cellular, military radar, and other wireless communications applications. At lower frequencies, mature BiCMOS processes are typically used for these mixed signal, analog/digital ICs. But at GHz frequencies, loss and distortion increases, performance degrades, creating a need for special techniques.
Consider, for example, a 5G cell phone sending and receiving 28 GHz signals to and from a cell tower. R/F signal circuitry in the phone and the tower is required to manipulate these 28 GHz signals in various ways, including switching between transmit and receive (T/R) mode. The circuitry that implements these T/R switches must operate at high frequency, with good isolation in the off state, and without introducing signal loss or degradation. This presents challenges for classical BiCMOS design processes, which fare poorly in these measures.
Problems With Traditional Bulk NMOS Transistors
Analog designers are familiar with the use of metal-oxide-semiconductor field effect transistors (MOSFETs) as switches for low frequency (or DC) signals. They allow a signal, passing through the drain-source channel, to be switched on or off with very small voltages, and negligible switching current. When a switching voltage applied from gate to source exceeds a threshold, VGS, the switch is turned on, and the path between drain and source has low impedance. Otherwise, the switch is off, and the drain-source path has high impedance.
However, at higher radio frequencies (RF), the channel cannot be switched completely off, because the capacitive paths from drain and source to the substrate (bulk) become significant, resulting in signal loss. This is shown schematically in Figure 1. Since the bulk is common to both the input and output signal in a series connected field effect transistor (FET), the input and output are capacitively coupled through the bulk. This limits the isolation offered by switches using standard NMOS devices.
Figure 1: Standard Bulk NMOS FET and equivalent circuit model showing parasitic conduction paths to substrate. Drain and Source cannot be fully isolated when the transistor is off.
Standard NMOS devices can also suffer poor linear response to signals, especially at higher amplitudes. As shown in Figure 1, parasitic diodes are formed between the bulk p material of the substrate and the n+ material of the source and drain. These diodes can be turned on by higher amplitude RF signals. This limits the allowable swing by clipping and distorting the signal.
The traditional way to overcome this problem is to place multiple transistors in series – a technique referred to as stacking. This configuration allows larger voltage swings, increased power handling, and reduced clipping and signal distortion. But at higher RF frequencies, the low impedance capacitive shunt paths become significant, preventing effective use of stacking.
In the last decade or so, a technically innovative and cost-efficient solution to the problems discussed above has been perfected and is now available in most modern semiconductor process technologies.
The solution is based on an enhancement to the standard BiCMOS process technology that involves an additional n layer implanted between the bulk and the substrate. Transistors built with this technology are referred to as triple-well devices.
Referring to Figure 2, a deep n-well is implanted between the p-well bulk and the p substrate, effectively isolating the bulk from the low resistance substrate. The two diodes formed by the deep n-well are the key to achieving this isolation. By using a positive voltage applied at the N-well terminal to reverse bias these diodes through a large resistor, the deep n-well becomes electrically floating, thereby isolating the p-well bulk from the p substrate.
This has several benefits, discussed in the sections below.
Figure 2: Triple-well NMOS FET, showing n-well and bulk bias terminals, and equivalent circuit model. The reverse biased N-well diodes isolate the bulk from the substrate.
Clipping and Distortion
The first benefit is near elimination of the clipping and distortion that occurs in standard bulk NMOS transistors under large RF signal swings. By isolating the bulk from the substrate and floating the bulk to ground through a large resistor, RB, the p-well source and drain diodes are effectively prevented from turning on. This eliminates the nonlinear junctions of standard bulk NMOS transistors, resulting in less signal distortion under large RF swings.
High Frequency Isolation
Isolating the p-well bulk from the low resistance p substrate also improves source drain isolation when the transistor is in the off state. Referring to Figure 2, the capacitive coupling between source and drain (CSB and CDB) appears in series with a large resistance to ground (RB). This minimizes the high frequency RF leakage; improves the isolation between the source and drain terminals of the switch.
The use of triple-well NMOS devices can also improve the performance of stacked transistors under higher RF signal swings. By floating the p-well body through the RB resistor (Figure 2), and isolating the body from the substrate, losses through the capacitive shunt paths are reduced, thereby enabling the desirable features of transistor stacking – improved power handling, larger signal swings, and less distortion.
Triple-well NMOS devices also provide benefits for mixer applications, prevalent in base station radio receivers. Mixers are used to down-convert an RF signal to an intermediate frequency (IF) signal and must have good noise characteristics (low noise figure) with low-distortion. Mixer designs can take advantage of triple-well NMOS devices in the following manner. Instead of grounding the p-well bulk terminal through a resistor, RB in Figure 2, the p-well bulk terminal is connected through a large resistor directly to the source terminal. As before, the positive voltage on the deep N-well terminal keeps the N-well diodes reverse biased, isolating the p-well bulk from the p-substrate. This reduces shunt capacitance and RF signal loss. The use of a large resistor between the bulk and source terminals keeps the p-well floating at RF frequencies, thereby reducing the diode clipping, and reducing signal distortion.
Because of these characteristics, the use of triple-well devices provides an economical approach to designing mixers with low loss, and low distortion.
This article has identified some of the problems that emerge with high frequency RF signal switching circuits on BiCMOS ICs using standard CMOS devices, and it has shown how triple-well devices can address some of those problems.
Triple-well devices are an important enabling technology for ICs that process higher frequency RF signals. Since they require minimal extensions to standard BiCMOS processes, they provide an economical solution to the problems introduced by increasingly higher frequency signals used by modern communications technologies. They do, however, introduce design subtleties that must be carefully addressed. Intrinsix has successfully implemented triple-well devices to solve challenging R/F microwave design challenges resulting in many first pass silicon successes.
- J. Li and Y. P. Zhang, “Flipping the CMOS switch,” IEEE Microwave Magazine, vol. 11, no. 1, pp. 86-96, 2010.
- Krishnamurthi, Z. Liu and I. Gresham, “Design of linear SiGe IC downconverters”, Microwave Journal, March 2013.