>This position can be fully remote from anywhere in the United States.<
>This position can also be based out of the Marlborough, Massachusetts Design Center in a hybrid model.<

SoC Architect/Technical Lead, Digital ASIC & SoC

[Updated 30 March 2023]

• 12+ years of experience in High-Performance ASIC & SoC development and familiarity with the semiconductor and microelectronics ecosystem for both defense and commercial industry.
• Hands-on knowledge in all phases of the ASIC process (design and simulation through GDSII hand-off) and industry-standard EDA tool flows, such as Cadence, Synopsys, and Mentor.
• High level of expertise in IP core integration, such as DSP, RISC, CPU and GPU, with experience evaluating tradeoffs in PPA (power, performance, area) and cost for design optimization.
• Broad understanding of semiconductor/solid-state physics with experience in physical design and layout.
• Experience with a wide variety of semiconductor fabrication vendors and process nodes/technologies.
• Significant experience with synthesis, STA, and DFT ASIC design and verification sign-off methodologies.
• Proficient in RTL coding (Verilog and VHDL) and SystemVerilog.
• Proficient in C/C++, Perl, Tcl/Tk, Python, assembly language, UNIX/Linux, and shell programming.
• Excellent communication skills with significant experience in writing technical proposals and making technical presentations to customers.
• Proven track record of efficacy in technical leadership and team management.
• Eligibility for Confidential, Secret, or Top Secret security clearance preferred.
• East Coast/Eastern Time Zone preferred.

Minimum Requirements:

• Bachelor's or Master’s Degree in Electrical Engineering, Computer Engineering, or equivalent with at least 10 years of direct hands-on experience in ASIC/SoC and FPGA design; or
• Ph.D. with at least 8 years of experience and excellent professional recommendations.
• Experience must be recent, working in this industry or role within the past 2 years.
• Must be able to communicate technical concepts fluently in written and spoken English.
• Must have permanent legal authorization to work in the U.S. without employer sponsorship.*
• Applicant must be a U.S. Person.**
• Must currently reside in the United States. 
• Ability to work in a fully remote capacity with occasional travel to the Intrinsix Design Center or other U.S. and international CEVA locations.

* Intrinsix cannot sponsor visas at this time.

** Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE. ANY UNSOLICITED RESUME OR CANDIDATE THAT IS SENT TO INTRINSIX WILL NOT BE SUBJECT TO ANY REFERRAL FEES OR OTHER OBLIGATIONS.

This is a full-time position based out of the Marlborough, Massachusetts Design Center.

[Updated May the 4th 2023]

New Graduate Design Engineer

Intrinsix Corp. is seeking new, recent, or soon-to-be EE and ECE graduates to join our VLSI hardware and embedded software team. You will be an engineering team member engaged in all aspects of custom IC (integrated circuit) design projects. You will have opportunities to join teams performing analog/mixed-signal circuit design, digital logic design, digital and mixed-signal verification, IP development, and hardware-interfacing software development. You will become an expert user of industry-standard IC design and verification tools from Cadence. 

Qualifications:

• BS or MS degree(s) in Electrical Engineering, Electrical & Computer Engineering, Robotics Engineering, Computer Science, or closely related discipline.
• Ability to quickly learn new concepts, tools, and methodologies. 
• Proven ability to work in a team environment.
  
• Strong candidates will have industry internship experience.

• Calculus/Differential Equations
• Digital and/or Analog Logic Design
• Microelectronic Circuits I & II
• Circuit Theory/Circuit Analysis
• Embedded Computing
• Object-Oriented Design/Programming with Python
• C/C++ Programming
• Verilog and/or VHDL
• FPGA/Programmable Logic Device Design
  

Requirements:

• Applicant must have permanent legal authorization to work in the U.S. (Intrinsix cannot sponsor work visas at this time.)
• Strong communication skills with fluency in English, both written and verbal.
• Applicant must be a U.S. citizen, U.S. Permanent Resident, or an individual otherwise granted asylum or refuge in the United States under an amnesty program.*

Please note: This position will be based out of the Marlborough, Massachusetts office and will require the engineer to reside in the Greater Boston area for the first 1-2 years of employment.

* Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE.

> This position can be fully remote from anywhere in the United States.
> This position can also be based out of the Marlborough, Massachusetts Design Center in a hybrid model.
> Short-term project-based contractor positions may also be available.

[Updated 4 May 2023]

Senior/Principal-level Lead Physical Design & Layout Engineer, Digital ASIC/SoC

Intrinsix is seeking an expert Digital and Mixed-Signal ASIC/SoC Physical Design and Layout Engineer to be a hands-on technical contributor and team leader in the design and layout of standard cells for both full-custom and semi-custom ASICs. Intrinsix ASICs and SoCs are designed for end-use in many diverse industries such as aerospace and defense, medical and biotech, autonomous driving, finance, Internet of Things, telecommunications, and consumer electronics.

As a Principal Physical Design Engineer at Intrinsix, you will collaborate with the front-end ASIC engineering teams, utilizing your experience to lead and execute full-chip layout design, block-level floorplanning and partitioning, and analysis and design of I/O rings, pad placement, bump planning, and distribution layers. You will craft innovative layout solutions and create custom wiring for complex ASIC & SoC designs implemented in a variety of advanced process nodes and state-of-the-art technologies. This position can be based out of the Marlborough, Massachusetts Design Center, or can be a work-from-home/remote position for highly experienced engineers living in other areas of the United States. Dependent on your prior experience and career goals, this position could entail managing and growing a team of engineers.

Qualifications and Skills:

• 10+ years of experience in transistor-level design and layout of Digital and Mixed-Signal integrated circuits and systems-on-chip with broad experience in a wide variety of leading-edge technologies and foundry processes for high-performance Mixed-Signal SoCs.
• Experience must be recent, working in this industry or role within the past 3 years.
• Significant experience with layout in sub-28nm nodes and FinFET architectures is required. Advanced node experience (10nm, 7nm, 5nm) is highly desirable.
• Broad understanding of the entire ASIC development cycle, with hands-on experience in the backend flow including: Floorplanning, Power Planning, CTS (Clock Tree Synthesis), PNR (Placement and Routing), Parasitic Extraction, STA (Static Timing Analysis), timing closure, Power Analysis (including EM/IR), Post-layout simulation, and Physical verification (including DRC and LVS).
• Significant experience using industry-standard methodologies and EDA tool flows, with expert-level fluency using the Cadence Innovus tool flow and Mentor Calibre highly desired.
• Proven track record of on-schedule delivery of layout blocks and/or macros following top-down strategy and specifications.
• Proven ability to address and resolve layout issues such as Multi-Vt design, EM (electromigration), ESD protection, current density and leakage current issues, IR drop and power distribution issues, signal coupling and parasitic inductance, simultaneous switching noise, peak/average/RMS power, and global vs. local variations.
• Experience with PNR of standard cells for embedded CPU cores, NoC fabric, datapath blocks, ALUs, etc.
• Ability to work outside the tools for modification of standard flows, scripting, and automating processes to achieve improvement in physical design methodology.
• Experience with Verilog/VHDL coding, Python, Perl/Tcl scripting, and UNIX/Linux is preferred.
• Excellent communication skills with experience writing technical documentation is preferred.
• Proven track record in technical leadership and mentoring junior engineers is highly desirable.
• Eligibility for Confidential, Secret, or Top Secret security clearance is preferred.

Minimum Requirements:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or equivalent with at least 12 years of direct hands-on industry experience in Digital ASIC and Mixed-Signal SoC physical design; or
• Master’s Degree with at least 10 years of experience.
• Must be able to communicate technical concepts fluently in written and spoken English.
• Must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.* (Intrinsix cannot sponsor work visas at this time.)

*Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE. ANY UNSOLICITED RESUME OR CANDIDATE THAT IS SENT TO INTRINSIX WILL NOT BE SUBJECT TO ANY REFERRAL FEES OR OTHER OBLIGATIONS.

> Can be a fully remote position or an on-site/hybrid model out of the Greater Boston area.*

[Updated 28 Sept 2022]

Senior Design Engineer, Analog/ Mixed-Signal/RFIC & SoC

Intrinsix is seeking a highly experienced Analog, RF, and Mixed-Signal ASIC/SoC design engineer to provide technical management on customer projects. You will provide hands-on leadership taking projects from inception to completion. You will analyze customer requirements, create specifications, and architect integrated solutions for end-use in many diverse industries such as aerospace and defense, medical and biotech, autonomous driving, finance, Internet of Things, telecommunications, and consumer electronics.

You will serve as a customer-facing technical expert to assist with pre-sales business development and proposal writing, helping to define project scope and tasks. You will craft innovative solutions for complex ASIC & SoC design problems, implementing designs in a variety of advanced process nodes and state-of-the-art technologies. You will integrate existing IP blocks into new designs, contribute to internal research activities, and have opportunities to develop new patents with Intrinsix. You will evaluate team and individual performance, completing post-project debrief and lessons learned documentation. Dependent on your prior experience and career goals, this position will entail managing and growing a team of engineers. This position has potential to grow into a department-level director role as well.

Qualifications and Skills:

• 5+ years of experience transistor-level design and verification of Analog/RF and Mixed-Signal integrated circuits and systems, and familiarity with the semiconductor and microelectronics ecosystem for both defense and commercial industry.
  
• Hands-on knowledge in all phases of the Mixed-Signal ASIC flow (design and simulation through GDSII hand-off) using industry-standard methodologies and EDA tool flows (Cadence, Synopsys, and Mentor).
• Proficient in Mixed-Signal simulation and verification techniques, including SPICE/Multisim.
• Significant experience with A/D converters including SDM (Sigma-Delta Modulator) design, complex op-amp architectures, oscillators, PLLs, and digital filters (FIR, IIR, Decimation, Interpolation, Multi-rate, etc.).
• Understanding of the math associated with linear transforms and quantization theory.
• Proficient in Verilog/Verilog-AMS, C/C++, Python, Perl, Tcl/Tk, MATLAB, UNIX/Linux, and shell scripting.
• High level of expertise in IP core integration in Mixed-Signal SoCs with experience evaluating tradeoffs in PPA (power, performance, area) and cost for design optimization.
• Broad understanding of semiconductor/solid-state physics with experience in physical design and layout.
• Broad understanding of IC processing technologies and experience with a wide variety of semiconductor fabrication vendors and advanced process nodes for high-performance Mixed-Signal SoCs.
• Excellent communication skills with significant experience writing technical proposals and making technical presentations to customers.
• Proven track record in technical leadership, team management, and mentoring junior engineers.
• Experience with mmWave/high frequency (>20GHz) is highly desirable.
• Experience in the design of ROICs and imaging sensors is highly desirable.
• Eligibility for Secret/Top Secret security clearance preferred.

Minimum Requirements:

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or equivalent
• 5+ years of direct hands-on experience in Analog/RFIC and Mixed-Signal SoC design (or Ph.D. with at least 2 years of industry experience).
• Experience must be recent, working in this industry or role within the past 2 years.
• Must be able to communicate technical concepts fluently in written and spoken English.
• Must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.*
• Must currently reside in the United States or relocate to the area on or before 12/31/2022. 
  

*Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE.

> This will be a full-time position with Intrinsix based out of our Marlborough, Massachusetts Design Center. 

[Updated 28 Sept 2022]

Senior FPGA, Embedded Software Engineer & Security Architect

Intrinsix is seeking a highly experienced and versatile embedded software engineer with extensive software experience very close to the hardware. Experience with hardware-level/firmware and software security architecture, design, testing, and analysis is desired to perform ASIC and SoC development alongside the hardware design team.

As a Senior/Principal FPGA & Embedded Software Engineer, you will design embedded software and firmware for SoCs, ASICs, and FPGAs, including definition and implementation of advanced architectures for real-time embedded processing. You will work with the ASIC design and verification team throughout architecture definition, design implementation, and functional verification phases.  In addition, you will participate in lab bring-up/debug of engineering prototype hardware.  Code development responsibilities include: board support packages, bare metal device drivers, boot code, hardware diagnostics, BIOS development, and RTOS interfacing.

Qualifications:

• 8+ years of experience in real-time embedded systems software development for FPGA, ASIC, and SoC.
• Experience must be recent, working in this industry or role within the past 2 years.
• 5+ years of experience with UNIX/Linux and Windows operating environments.
• Experience with embedded processor (CPU/DSP) core code development.
• Experience using test equipment to test and verify the performance of hardware.
• Experience debugging hardware in a lab environment utilizing test equipment (scopes/analyzers).
• Experience writing detailed software specifications.
• Proficient in C, C++, Python, Perl, Tcl/Tk, assembly programming, and Verilog RTL code development.
• Familiarity with ARM and Tensilica ISA and HW architecture highly desirable.
• Experience in FPGA development/verification using VHDL/System Verilog/UVM and OVM is highly desired.
• Experience modeling and simulating using PSPICE, MATLAB/Simulink is preferred.
• Experience with hardware-level and firmware security architecture, design, testing, and analysis highly desired.
• Eligibility for Secret/Top Secret security clearance preferred.

Minimum Requirements:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or equivalent with at least 10 years of direct hands-on experience in ASIC/SoC and FPGA design; or
  Master’s Degree with at least 5 years of experience.
• Must be able to communicate technical concepts fluently in written and spoken English.
• Must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Must currently reside in the Northeastern United States or relocate to the area on or before 12/31/2022. Greater Boston area/Middlesex County in Massachusetts preferred.
  
• Applicant must be a U.S. Person.*

*Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE.

Will be on-site/hybrid model out of the Greater Boston area, or a fully remote position if based in other areas of the U.S.

[Updated 28 Sept 2022]

Sr./Principal-level Verification Engineer, Digital/Mixed-Signal ASIC

Provide hands-on technical contribution and leadership on ASIC/SoC and IP development projects. Help architect, specify, and lead the implementation of verification projects using high-level verification languages and industry standard verification methodologies. Work very closely with ASIC/SoC project leaders to implement complete verification environments and methodologies. Analyze customer technical requirements, propose solutions, and work collaboratively in a multi-site development environment.

Qualifications:

• 7+ years of experience in ASIC/SoC verification in a team environment.
• Experience must be recent, working in this industry or role within the past 3 years.
• Experience architecting verification environments and writing test specifications.
• Ability to lead a small verification team, and work collaboratively in a multi-site development environment.
• Extensive applied knowledge of SystemVerilog and UVM.
• Hands-on experience using Object-Oriented Programming (OOP) techniques, random test generation, assertion-based verification, and functional coverage.
• Proficiency in C and experience with Perl, Tcl, Make, UNIX scripting.

Requirements:

• Applicant must have a minimum of 5 years direct experience in ASIC design verification.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.*

* Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE.

> Can be a fully remote position or an on-site/hybrid model out of the Greater Boston area.

> Short-term project-based contract positions may also be available.

[Updated 28 Sept 2022]

Sr./Pr. Analog & Mixed-Signal ASIC Layout Engineer

Intrinsix Corp., a wholly owned subsidiary of CEVA, Inc. is looking for a highly experienced Analog & Mixed-Signal Layout Engineer to act as a team lead in the layout of cutting-edge ASICs and SoCs, from initial planning with the front-end design team to final GDSII/OASIS sign-off. In this role you will be a hands-on technical contributor in transistor-level IC design and layout of standard cells for full custom ASICs. You will solve external customers’ design problems while developing internal A/MXS and RFIC IP such as temp sensors, SERDES/data converters, and PLLs.

You will guide and implement full custom analog and mixed-signal designs at the cell, block, and chip levels. Through your participation in a variety of projects you will bring designs to tape-out, implementing cutting-edge ASIC and SoC layout methodologies & enabling efficient design flows within the Cadence Virtuoso suite.

If you are up for a challenge of working for an international U.S.-based technology company and have most of the technical skills and experience listed below, we look forward to reviewing your application!

RESPONSIBILITIES:

• Serve as Team Lead, collaborating with the design team on analog/mixed-signal layout for high-performance analog circuits including ADC/DACs, PLLs, Op-Amps, LDO regulators, oscillators, etc.
• Complete layout tasks and address issues such as multi-Vt design, electromigration, current density issues, IR drop, and power distribution issues.
• Consider trade-off analysis/optimization and common layout issues (noise, power vs. performance, dynamic range, device mismatch, etc.) in back-end design for analog/mixed-signal, RFIC, and SoC projects.
• Foster strong relationships with all team members and engineering leadership.

QUALIFICATIONS & SKILLS:

• 5+ years of experience in transistor-level IC design and layout of complex analog circuits; RF circuit experience a plus.
• Comfortable using current version of the Cadence® Virtuoso® XL or GXL Layout Suites (IC6.1.n and Virtuoso Advanced Node ICADVM18.n).
• Familiarity with trade-off analysis/optimization and common layout issues such as noise, power vs. performance, dynamic range, device mismatch, etc.
• Experience with advanced nodes and innovative layout methodologies, including FinFET and deep sub-micron CMOS technologies.
• Familiarity with Mentor Calibre verification tool.
• Experience scripting/developing solutions to automate analog layout functions is a plus.
• Demonstrated ability to get the job done with minimal direction/supervision.
• Excellent management and communication skills with the ability to mentor and develop staff while interfacing effectively with upper management and external customers.
• Demonstrated ability to plan, organize, and prioritize tasks to meet deadlines and drive initiatives to completion.

MINIMUM REQUIREMENTS: (Candidates must meet the following criteria to be considered.)

• Associate’s or Bachelor’s Degree in Electrical or Computer Engineering (or an equivalent course of training with at least 5 years of custom ASIC/SoC design and integration).
• Must be able to communicate with native-level fluency in written and spoken English.
• Ability to work efficiently from home utilizing video-/audio-conferencing technologies (Zoom, Microsoft Teams, etc.).
• Must be a U.S. person with permanent authorization to work and reside in the United States. *

* Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3). Intrinsix does not currently sponsor work visas.

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE.

[Updated 28 Sept 2022]

Candidate will be a hands-on technical contributor and leader in verification of mixed-signal ASIC projects. Candidate will help architect, specify, and lead the implementation of mixed Analog/Digital design verification efforts using analog and digital simulation tools including high-level verification languages.

Qualifications:

• 5+ years of experience in mixed-mode verification in a team environment.
• Experience with analog and digital test generation and familiarity with metrics-driven verification and functional coverage methodology.
• Experience with writing test plans and architecting verification environments.
• Extensive applied knowledge of SystemVerilog and UVM.
• Proficiency in Cadence AMS simulation environment including Spectre, APS, and Incisive.
• Experience with system-level modeling of Mixed-Signal, Analog, and RF systems with Simulink.
• Experience with Real Number Modelling (RNM) and Verilog-AMS.
• Experience with scripting languages (e.g. Make, Perl, Tcl).

Requirements:

• Applicant must have a minimum of 5 years direct experience in mixed-mode ASIC design verification.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.*

*Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE.

Candidate will work as a Project Manager for Mixed-Signal System-on-chip (SoC) development out of the Marlborough, Massachusetts Design Center. Will participate in ASIC and SoC developments from initial formulation of customer proposals and on-going supervision of the Intrinsix design effort, to relationship management between Intrinsix and our clients, including third-party design partners. Will oversee all aspects of project management using planning, monitoring, and controlling processes in the design of cutting-edge custom analog, mixed-signal, and radio-frequency integrated circuits.

Qualifications:

• 5+ years of recent experience in electronics design and development engineering with focus on ASIC design and integration, including at least 2 years of project management experience.
• Experience must be recent, working in this industry or role within the past 3 years.
• Proven track record coordinating the efforts of local and remote hardware design teams for Analog/Mixed-Signal and RFIC projects.
• Proven technical leadership abilities with experience in team building, process improvement, conflict resolution, and motivating people.
• Proven track record in using project management techniques to coordinate the efforts of hardware design teams.
• Skilled in developing Risk Register and Risk Response plans, using pricing models and billing procedures for budget management, and communicating to management the status of resource utilization, project costs, risk management, project profit margins.
• Skilled in Microsoft Project, Microsoft Office (Word, Excel, PowerPoint), and Microsoft SharePoint.
• Master's Degree is highly desirable.

Strong candidates will also have one or more of the following:

• Significant experience with supply chain management.
• Significant experience with mmWave/super high-frequency RFIC and radar technologies.
• Experience writing technical proposals and giving technical presentations.
• Experience using Microsoft SharePoint for document sharing and storage, etc.
• Ability to obtain Confidential or Secret Security Clearance is a plus.

Requirements:

• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or an equivalent degree.
• Applicant must have at least 5 years of direct, hands-on experience in MXS or RFIC & SoC design, or other custom semiconductor device development.
• Applicant must be PMI certified or actively working towards PMP Certification.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must be a U.S. person.*
• Ability to work in a fully remote capacity with occasional travel.
• High level of competency communicating via video conferencing apps (Zoom, Teams, etc.).

*Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

INTRINSIX IS NOT ACCEPTING RESUMES FROM OUTSIDE RECRUITERS, THIRD-PARTY AGENCIES, OR STAFFING COMPANIES. NO PHONE CALLS OR EMAILS FROM RECRUITERS, PLEASE.