Updated 7 Dec 2018: 

This is an immediate opening for a full-time position.

Candidate will be a hands-on technical contributor and leader in verification of mixed-signal ASIC projects. Candidate will help architect, specify, and lead the implementation of mixed Analog/Digital design verification efforts using analog and digital simulation tools including high-level verification languages.

Qualifications:

• 5+ years of experience in mixed-mode verification in a team environment.
• Experience with analog and digital test generation and familiarity with metrics-driven verification and functional coverage methodology.
• Experience with writing test plans and architecting verification environments.
• Extensive applied knowledge of SystemVerilog and UVM.
• Proficiency in Cadence AMS simulation environment including Spectre, APS, and Incisive.
• Experience with system-level modeling of Mixed-Signal, Analog, and RF systems with Simulink.
• Experience with Real Number Modelling (RNM) and Verilog-AMS.
• Experience with scripting languages (e.g. Make, Perl, Tcl).

Requirements:

• Applicant must have a minimum of 5 years direct experience in mixed-mode ASIC design verification.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person. 

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Responsibilities include design and implementation of embedded software/firmware for SoC ASICs and FPGAs, including definition and implementation of advanced architectures for real-time embedded processing. You will work with the ASIC design and verification team throughout architecture definition, design implementation, and functional verification phases.  In addition, you will participate in lab bring-up/debug of engineering prototype hardware.  Code development responsibilities include: board support packages, bare metal device drivers, boot code, hardware diagnostics, BIOS development, and RTOS interfacing.

Qualifications:

• 8+ years of experience in real-time embedded systems software development
• 5+ years of experience with Linux and Windows operating environments
• Experience with embedded processor (CPU/DSP) core code development
• Experience using test equipment to test and verify the performance of hardware
• Experience debugging hardware in a lab environment utilizing test equipment (scopes/analyzers)
• Experience writing detailed software specifications
• Proficient in C, C++, and assembly programming
• Familiarity with Verilog RTL
• Familiarity with ARM and Tensilica ISA and HW architecture highly desirable
• Experience in FPGA development/verification using VHDL/System Verilog/OVM is a plus
• Experience modeling and simulating using PSPICE, MATLAB/Simulink is a plus

Requirements:

• Applicant must have a minimum of 5 years direct experience in embedded software and firmware development for integrated circuits and/or FPGAs.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or an equivalent field of study.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Provide technical leadership on customer projects. Provide technical support in analyzing customer requirements, while architecting and proposing solutions. Craft state-of-the-art solutions for complex Analog and Mixed-Signal ASIC and SoC design problems. This position may entail managing and growing a team of engineers.

Qualifications:

• 10+ years of experience in transistor-level design and verification of Mixed-Signal, Analog, and RF circuits and systems.
• 5+ years of experience in design of ROICs and imaging sensors/detectors
• Hands-on knowledge of all phases of the Mixed-Signal ASIC process (design and simulation through GDSII hand-off).
• Proven track record in technical leadership and team management.
• High level of expertise in Mixed-Signal tools and methodologies.
• Broad knowledge of IC processing technologies and Solid-State Physics.
• Excellent communication skills with significant experience in writing technical proposals and making technical presentations to customers.

Strong candidates will also have one or more of the following:

• Experience in ROIC designs for automotive applications
• Expertise in physical design and analog layout
• Knowledge of the math associated with linear transforms and quantization theory
• Experience with A/D converters including Sigma-Delta Modulators
• Broad knowledge of digital filters (FIR, IIR, Decimation, Interpolation, Multi-rate)

Requirements:

• Applicant must have at least 5 years of direct, hands-on experience in mixed-mode ASIC design and ASIC/SoC development.
• Applicant must have a Master’s Degree or Ph.D. in Electrical Engineering, Computer Engineering, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.
• Ability to obtain Secret Clearance highly desirable.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Function as a team mentor and individual contributor during all project phases, including transistor-level design, simulation, and layout of analog cells as well as system-level verification of Analog/Mixed-Signal and RF ASICs. Create and modify transistor-level circuit designs for highly complex analog, RF, and mixed-signal ASICs. Run a variety of simulation tools including Cadence Virtuoso to perform schematic capture and simulations. Work with layout engineer to floor plan ASIC blocks and provide guidance on requirements for physical layout.

Qualifications:

• 8+ years of experience in transistor-level design and verification of Mixed-Signal, Analog, or RF circuits and systems.
• 2+ years of experience in design of ROICs and imaging sensors/detectors
• Experience with system-level architecture and behavioral modeling of Mixed-Signal, Analog, and RF systems.
• Broad knowledge of IC processing technologies and Solid-State Physics.
• Broad knowledge of digital filters (FIR, IIR, Decimation, Interpolation, Multi-rate).
• 2+ years of project leadership experience with in-depth understanding of ASIC design cycle.
• Applied knowledge of all phases of the ASIC process (design and simulation through GDSII hand-off).
• Experience in the writing and presentation of technical proposals and project status reports.

Requirements:

• Applicant must have a minimum of 5 years direct experience in ASIC design.
• Applicant must have a Master’s Degree or PhD in Electrical Engineering, Computer Engineering, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. person.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Provide leadership as a hands-on technical contributor in the development and implementation of Design-for-Testability (DFT) features to support post-silicon test, debug, and characterization for leading-edge ASIC/SoC design projects at advanced 22nm and 16/14nm nodes. Lead the DFT effort using industry-standard methodologies, create DFT architecture/partitioning, and lead the DFT specification development. Implement chip test methods for failure analysis and fault isolation to resolve test pattern and coverage issues and support the physical design/layout team for the integration of DFT structures into the ASIC design.

Qualifications:

• 5+ years of experience in complex high-speed ASIC/SoC DFT implementation.
• Previous experience in DFT implementation using front-end and back-end EDA tool flows (Cadence, Mentor, or Synopsys).
• Experience performing full scan, partial scan, boundary scan, BIST, MBIST (Memory BIST), test vector generation, transition fault test, and bridge fault testing.
• Expertise in ATPG and DFT design at advanced nodes is a plus (22nm, 16/14nm).
• Proficient in Verilog and scripting languages (Perl, Tcl, C/C++).
• Hands-on experience in RTL design and synthesis for custom test logic.
• Experience writing technical documents and design specifications.

Requirements:

• Applicant must have a minimum of 10 years of direct experience in ASIC/SoC design.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Serve as an ASIC/SoC/FPGA Lead Design Engineer. Provide hands-on technical design leadership and be an individual contributor on ASIC/SoC and FPGA projects. Hold responsibility for, and contribute to, all phases of an ASIC/SoC/FPGA development starting from creation of an architectural specification through ASIC/SoC/FPGA sign-off. 

Qualifications:

• 10+ years of experience in high-speed ASIC/SoC/FPGA development.
• Previous experience as ASIC/SoC/FPGA design lead.
• Proficient in Verilog.
• Experience with deep-submicron CMOS technologies and a wide variety of ASIC/FPGA vendor technologies.
• Significant experience with synthesis, static timing analysis (STA), and DFT ASIC vendor sign-off methodologies, including Cadence and Synopsys tool flows.
• Knowledge of embedded processor architectures.
• Experience in writing technical specifications as well as technical proposals and project status reports.
• Experience in fixed-point hardware DSP modeling using MATLAB Simulink is a plus.
• Verification experience is a plus.

Requirements:

• Applicant must have a minimum of 5 years of direct experience in ASIC design.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Provide hands-on technical contribution and leadership on ASIC/SoC and IP development projects. Help architect, specify, and lead the implementation of verification projects using high-level verification languages and industry standard verification methodologies. Work very closely with ASIC/SoC project leaders to implement complete verification environments and methodologies. Analyze customer technical requirements, propose solutions, and work collaboratively in a multi-site development environment.

Qualifications:

• 7+ years of experience in ASIC/SoC verification in a team environment.
• Experience architecting verification environments and writing test specifications.
• Ability to lead a small verification team, and work collaboratively in a multi-site development environment.
• Extensive applied knowledge of SystemVerilog and UVM.
• Hands-on experience using Object-Oriented Programming (OOP) techniques, random test generation, assertion-based verification, and functional coverage.
• Proficiency in C and experience with Perl, Tcl, Make, UNIX scripting.

Requirements:

• Applicant must have a minimum of 5 years direct experience in ASIC design verification.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Provide technical leadership on customer projects. Provide technical support in analyzing customer requirements, while architecting and proposing solutions. Craft state-of-the-art solutions for complex ASIC & SoC design problems. Dependent upon candidate’s prior experience, this position may entail managing and growing a team of engineers.

Qualifications:

• 15+ years of experience in High-Performance ASIC & SoC development.
• High level of expertise in IP core integration, such as DSP, RISC CPU and GPU.
• Hands-on knowledge of all phases of the ASIC process (design and simulation through GDSII hand-off).
• Proven track record in technical leadership and team management.
• Experience with a wide variety of semiconductor fabrication vendors.
• Broad knowledge of IC processing technologies and Solid-State Physics.
• Significant experience with synthesis, STA, and DFT ASIC design and verification sign-off methodologies.
• Proficient in SystemVerilog.
• Excellent communication skills with significant experience in writing technical proposals and making technical presentations to customers.
• Expertise in physical design is preferred.

Requirements:

• Applicant must have a minimum of 5 years direct, hands-on experience in ASIC/SoC design and development.
• Applicant must have a Master’s Degree or Ph.D. in Electrical Engineering, Computer Engineering, or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

Participate in IC developments from initial formulation of customer proposals and on-going supervision of the Intrinsix design effort, to relationship management between Intrinsix and our clients, including third-party design partners. Coordinate with the technical leads to develop project Statement of Work, Work Breakdown Structure, and specific project tasks and milestones. Oversee all aspects of project management using planning, monitoring, and controlling processes, as you balance technical, schedule, resource, and budget constraints.

Qualifications:

• 15+ years of experience in electronics engineering with focus on IC design and integration, including at least 5 years of project management experience.
• Proven technical leadership abilities with experience in team building, process improvement, conflict resolution, and motivating people.
• Proven track record in using project management techniques to coordinate the efforts of hardware design teams.
• Skilled in developing Risk Register and Risk Response plans, using pricing models and billing procedures for budget management, and communicating to management the status of resource utilization, project costs, risk management, project profit margins.
• Skilled in Microsoft Project and Microsoft Office (Word, Excel, PowerPoint).
• Master's Degree is highly desirable.
• PMP Certification is highly desirable.

Requirements:

• Applicant must have at least 5 years of direct, hands-on experience in ASIC/SoC development.
• Applicant must have BSEE or equivalent.
• Applicant must be able to communicate technical concepts fluently in written and spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. person.

Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

In this role you will be a hands-on technical contributor in transistor-level IC design and layout of standard cells for full custom ASICs.

Responsibilities:

• Collaborate with the design team on analog/mixed-signal layout for high-performance analog circuits including ADC/DACs, PLLs, Op-Amps, LDO regulators, oscillators, etc.

• Familiarity with trade-off analysis/optimization and common layout issues such as noise, power vs. performance, dynamic range, device mismatch, etc.

Qualifications:

• 5+ years of experience in transistor-level IC design and layout of complex analog circuits. RF circuit experience is an added plus.

• Comfortable using the Cadence Virtuoso layout suite

Requirements:

• Applicant must have a minimum of 5 years of direct experience.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or equivalent course of training.
• Applicant must be able to communicate technical concepts fluently in written/spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person as defined under ITAR.*

*Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).

In this role you will be a hands-on technical contributor and leader in the design and layout of standard cells for both full custom ASICs, utilizing your experience in place and route and extraction.

Responsibilities:

• Block and chip-level floorplanning and partitioning
• PNR of standard cells for embedded CPU cores, NoC fabrics, datapath blocks, ALUs, multipliers, etc.
• On schedule delivery of layout blocks and/or macros following top-down strategy and specs
• Address layout issues such as Multi-Vt design, electromigration, current density issues, IR drop, and power distribution issues

• Familiarity with common layout issues (leakage current, signal coupling, parasitic inductance, simultaneous switching noise, peak/average/RMS power, global vs. local variations, etc.)

Qualifications:

• 5+ years of experience in transistor-level IC design and layout of standard cells
• Broad depth of knowledge and ASIC design experience in leading-edge technologies and foundries

• Comfortable using Mentor and Cadence parasitic extraction tools and the Cadence physical design platform
• Experience with advanced nodes (7nm, 14/16nm) is a plus.

Requirements:

• Applicant must have a minimum of 5 years of direct experience in ASIC design.
• Applicant must have a Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or equivalent course of training.
• Applicant must be able to communicate technical concepts fluently in written/spoken English.
• Applicant must have permanent legal authorization to work in the U.S. without employer sponsorship.
• Applicant must be a U.S. Person as defined under ITAR.*

*Pursuant to 22 CFR §120.15, a U.S. Person is defined as a U.S. citizen, a U.S. Legal Permanent Resident, or a Protected Person under the Immigration and Naturalization Act – 8 U.S.C.1324b(a)(3).