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Sigma-Delta ADCs for

Cost Effective Conversions

The Intrinsix Sigma-Delta Stereo ADCs for Cost Effective Conversions (SD-ADC-CEC) are part of the larger offering of Sigma-Delta IP available from Intrinsix. 

 

The family of SD-ADC-CEC is generated utilizing proprietary, patent-pending techniques within the Intrinsix SDM Refinery toolset.  A design methodology that is geared towards a digital CMOS process helps reduce cost, die size and power consumption.  A high Signal to Noise Ratio (SNR) is achieved by pushing the frequency of the quantization noise outside the band of interest.  The challenge in Sigma-Delta ADC design is the "shaping" of this noise, which is characterized by the Noise Transfer Function (NTF), and the design of efficient filters to attenuate the noise.  The SDM Refinery automates this process:  The engineer specifies an Over-Sampling Ratio (OSR), quantization levels, order of complexity and SDM Refinery creates the desired ADC.

 

Intrinsix SD-ADC-CEC  are:

*    Perfect for applications that require low cost data converter technology, such as:

  • High Volume Consumer (Toys, MP3 Players, Cell Phones, etc)

  • Musical Instruments

  • Audio Feedback Controls (Home, Auto, etc)

*    Cost effective design geared for aggressive consumer market

*    Silicon proven architectures can be incorporated in a variety of CMOS-based silicon technologies:

  • TSMC, SMIC, UMC and Chartered (portable to any appropriate vendor)

  • .180μm and .250μm

*    Available in 16 and 20-bit resolutions

*    Available in 3rd and 4th Order  SD Modulation Complexity

       (others available upon request)

*    Able to achieve a Signal-to-Noise Ratio (SNR) of 105db

*   Compact design resulting in small die area

*   Very low in power consumption with a customizable Low Power Mode

*    Highly tunable for each application

*    Available as RTL and GDSII as well as RTL and Behavioral System models in industry

       standard formats such as Verilog-A or Simulink

  
     

Copyright Intrinsix Corp. 2008