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Intrinsix Corp. offers two standard versions of its VGA compatible HDL synthesizable core. The INT416 SM (standard modes only) is a reduced gate count, basic VGA, version of the core. The INT416 SXGA (super XGA) is an enhanced version of the core but has a higher gate count. Both designs contain the identical VGA core that is fully hardware register compatible to the IBM VGA standard. The SXGA is compatible to the VESA standards for the enhanced operating modes: 800x600, 1024x768, and 1280x1024, at refresh rates up to 85Hz. Table 1 provides a complete description of the supported display modes. Also included in both versions of the core is a IBM PS/2 compatible RAMDAC (i.e. the digital portion of the RAMDAC. The host interface and color LUTs. The video DAC module is not included).
Both versions of the core area are available in netlist or behavioral Verilog source code format. The design is modular with all inter-module signals and RTL fully documented. Modifications can be made to any area of the design in order to ease the integration task. Detailed core specifications including interface timing diagrams are available. Core are supported with a Verilog based test bench.
Both versions of the core have been implemented in Xilinx FPGA technology (Virtex, VirtexII, Virtex4, and Spartan3E. The architectural features of the Xilinx Virtex and Spartan FPGA series are mapped directly by the HDL code. The result is a highly efficient and low CLB count design. Timing constraints for synthesis and place/route are supplied with the core.
Both versions of the core have been implemented in .25um, .18um, and 90nm standard cell ASIC processes. Synopsys DC and Primetime flows have been utilized by customers. Maximum pixel clock rates are dependent on the target technology, but rates of 110MHz are achievable in .180um and 90nm.
Both the FPGA and ASIC implementations are suitable as standalone solutions, replacements for obsolete or soon-to-be obsolete parts such as the CHIPS & Technologies 82C451 Video Controller and can be surrounded by customer specific logic of your design or ours.
The architecture of the two versions of the core is very similar. There are three separate clock domains in the core, the host interface, the memory interface, and the video controller. Within these domains six primary blocks of logic make up the design. A block diagram of the INT416 SM core and INT416 SXGA core is shown above and a more detailed diagram with signal names and Verilog instance names is shown below.
Host Bus Interface
The cores support a generic request/grant CPU interface. This generic interface allows the core to be readily adapted to most industry standard buses (i.e. ISA, PCI, PCI-X, AMBA). The interface is synchronous with respect to the CPU system clock and has been characterized up to 200MHz. An external bus interface module is required in order to bridge between the core and the CPU bus. Intrinsix can supply bus interface modules to most of the PC standards. For graphics cards which are targeted to reside inside of Windows based PCs, the host interface must be capable of supporting legacy video.
All internal control and status registers of the core reside in the Host Interface. All registers are 8-bits wide, and are mapped into CPU I/O address space.
VGA CPU Memory Interface
The cores are designed to support a separate memory clock domain, which allows extreme flexibility in the specific type of memory technology used. Actual control of the memory system is left to an external memory arbiter and sequencer module. The interface from the core is a simple request/grant protocol, with control signals to convey information such as burst length, and bit masking. The data path is 64-bits wide. Designs have been completed with DRAM, SDRAM, and DDRAM controllers.
Third Party Host and Memory Controller Support
Intrinsix recommends the DDR Memory Controller and PCI Host Interface Controller IP blocks from Northwest Logic Design (www.nwlogic.com), which have been used successfully with the VGA cores.
VGA Scan Request Bus Interface
The SM and SXGA cores are similar in that the interface to the external memory arbiter/controller is a simple request/grant protocol. Also, both cores contain an internal video scan buffer which provides a FIFO like function between the video memory clock domain and the video clock domain. This organization directly supports high speed, bursting type DRAM technology such as DDR and DDR2. The SXGA supports programmable burst size and watermark settings for byte, word, and double word modes as well as alpha mode font burst size.
The size of the internal scan buffer is different in the two cores. Because the -SM version only needs to support the video bandwidth of standard VGA modes, it's scan buffer is a small register array. The SXGA however, utilizes internal RAM cells in order to support resolutions up to 1280x1024. The SXGA scan buffer consists of a block of 2-port RAMs. Write Logic and Read Logic format the data at both sides of the Scan Buffer. The Scan Buffer Read Logic in the SXGA also supports two output data paths. In VGA modes video data is supplied to the IBM compatible Video Attributes Controller as an 8-bit wide pixel data stream. In VESA compatible modes (support of high performance 3D) a 96-bit (16-bit for the SM) wide pixel data stream(4 pixels of 24-bits each) can be output to the external RAMDAC. The core can drive an external video DAC operating in either 1 pixel per clock or 4 pixels per clock mode.
The CRTC generates the monitor interface signals (hsync, vsync, and blank) and display memory addresses. This module consists of horizontal and vertical counters, sync.,blank and display format control registers. Monitor timing is highly programmable via the control registers (e.g. sync. position, width, blank position, width, pixels per line, lines per screen, etc.). In applications where the VGA core is used to supplement a higher performance graphic system (i.e. 3D engine) , the VGA CRTC can be used to provide monitor timing signals when either the VGA core is active or when the higher performance engine is active. CRTC resolution is based on a character time. Depending on the VGA mode this could be dotclk/8 or dotclk/9 (all graphic modes use dotclk/8, alpha modes use dotclk/8 or dotclk/9).
The Attributes Controller contains parallel-to-serial pixel data shift registers and the logic that controls specific display characteristics of the pixel data( e.g. foreground/background colors via the internal 16-word x 6-bit palette, cursor, underlining, and blinking). The output of the Attributes Controller drives the external RAMDAC (external to the VGA core). The both versions of the core support an external high speed pixel path that bypasses the internal attributes controller.
TABLE 1 VGA CORE VIDEO MODE
Note: SM Modes 0-13 only
Clocking Methodology and Synthesis Support
The Intrinsix VGA Core is a synchronous design capable of supporting a full scan methodology via ATPG and also full level sensitive scan implementations. The interface between the clock domains is asynchronous. In all cases signals that cross the asynchronous interface are defined as false paths. For ATPG the CPU clock and dot clock are tied to the same source. Synopsys constraint files are supplied for all lower level modules and the top level core module.
FPGA VGA Evaluation Platforms
To assist in the evaluation and integration of the VGA core, Intrinsix has available an ISA Bus VGA Demo Board (see Photo 1) and a PCI Bus SXGA Demo Board (Photo 2.)
On the ISA Bus VGA Demo Board resides a Xilinx Virtex FPGA (XCV300-BG432) that contains the VGA core, ISA bus interface, and DRAM memory controller. In addition the board has the Intrinsix VGA BIOS in Flash ROM and a PS/2 compatible RAMDAC. The demo board has a number of uncommitted I/O ports (which connect to test headers), unused switch inputs, and a Xilinx XChecker cable connector. Many system integrators have used the board as a development platform for the integration of the VGA with other application specific logic.
Photo 1, Intrinsix VGA Demo Board
Intrinsix VGA Core Simulation, Verification and Compatibility Testing
Intrinsix has also implemented the SXGA core into the Avnet Virtex-II Development Kit and plug-in Audio/Video Module. This is a PC compatible PCI/33 board that integrates the VGA core with the Northwest Logic DDR Controller and PCI Controller IP blocks.
The Intrinsix VGA core has undergone extensive verification in both a simulation environment, ASIC emulation, Xilinx platforms, and ASICs.
The VGA core has been confirmed to be compatible with Windows 95,98, NT, 2000, and XP.
Photo 2, SXGA Core on Avnet Virtex-II Development Board
EVC416 Test Program List
With each core a set of diagnostic and verification test programs is supplied. These programs are written in assembler and C. The following is a list of well known VGA test and compatibility programs that have been run on the EVC416 core.
1) Display Mate Video Display Utilities
2) VGA Compatibility Test Suite (Extensive VGA test suite)
3) Intel VGA Demo
6) Renaissance \ GRX VGA Compatibility and Diagnostic Tests.
7) Paradise VGA Challenge Test
8) PC Magazine PS/2 VGA Hardware Test Suite
10) Hercules VGA Demo
11) Programmers Journal, Michael Abrash VGA Test Programs
14) PC TECH Journal VGA Compatibility Tests
Intrinsix VGA Compatible BIOS
Also available from Intrinsix is a IBM VGA compatible video BIOS. This BIOS supports all of the standard IBM VGA BIOS functions and also extended video modes. The BIOS does not implement the current VESA extensions. For applications requiring full VESA support, the Intrinsix VGA core has successfully been tested with other 3rd party, VESA compatible, BIOS code. One such supplier is Elpin Systems.
Photo 3, Customer Integration of SM Core