SGMII eVC
SGMII e Verification Component
IP Part Number: DR924-SGMII-eVC
Features
-
SGMII compatible PHY or MAC interface
-
Modular, synchronous design
-
Compliant to the Cisco SGMII specification
-
Standalone mode for testing without simulator or RTL.
-
Integrated 8b/10b ENDECs
-
Full duplex
-
Compatible to Intrinsix SGMII to GMII Conversion Module
Applications
Ethernet switch, router and transceiver designs
Overview
The SGMII e Verification Component is part of a verification environment where a frame comprised of control and data code groups are input from a test or programming application and driven onto the Serial Gigabit Media Independent Interface (SGMII). The SGMII eVC is designed to support full state machine testing for transmit, receive, synchronization and auto-negotiation. The SGMII eVC will support operation in both half and full duplex, and at interface speeds of 10, 100 and 1000 Mb/s.
Interfaces
|
SGMII Interface |
||
|
Signal Name |
Direction |
Description |
|
RX+/- |
Input |
Received serial data at 1.25 GBaud synchronous to RXCLK. |
|
RXCLK+/- |
Input |
Receive clock , 625 MHz (DDR interface) |
|
TX+/- |
Output |
Transmit serial data at 1.25 Gbaud synchronous to TXCLK. |
|
TXCLK+/- |
Input |
Transmit clock, 625 MHz (DDR interface) |
|
|
||
|
Verification Environment Interface |
||
|
Structure Name |
Description |
|
|
DR924_sgmii_stream() |
Models a �frame� |
|
|
DR924_sgmii_tx() |
Responsible for driving frames into the DUT |
|
|
DR924_sgmii_rx() |
Processes serial data received from the DUT |
|
|
DR924_sgmiiRegisterSet() |
Contains control/configuration registers |
|
|
DR924_sgmii_config() |
Contains configuration information for using the ITRX_GMII_eVC |
|
|
DR924_sgmii_cover() |
Fields to generate Coverage information |
|
|
DR924_sgmii_error( |
The sgmii_error struct is used to inject errors |
|
|
DR924_sgmii_gen() |
Contains structs to control packet generation by SGMII_TX |
|
|
DR924_sgmii_signal_map() |
Defines the interface to the signals in the device under test ( DUT). |
|
|
DR924_sgmii_frames() |
Maintains a list of frames received |
|
|
DR924_sgmii_clocks() |
Clocks for standalone mode ONLY |
|
|
DR924_8B_10B() |
8b/10b encoder/decoder. Struct |
|
|
|
||
Method Name |
Description |
|
|
Post_generate() |
Generates frame for SGMII_TX |
|
|
TxReset() |
Resets SGMII TX |
|
|
drive_stream() |
Main TCM to drive data onto the SGMII interface (TX) |
|
|
SpeedSelect() |
Selects the link operation speed |
|
|
send_idle() |
Encodes/driver for Idle code groups |
|
|
send_config_idle() |
Encodes/driver for configuration ( autonegotiation ) code groups |
|
|
RxReset() |
Resets SGMII RX |
|
|
push_data() |
Collects received data bytes into a list |
|
|
receive_stream () |
Main TCM to receive data from the SGMII interface (RX) |
|
|
SerialTo10b() |
Converts serial data to 10b format |
|
|
log_message() |
Controls type of log messages to be displayed and/or included in log file |
|
|
|
||
|
Event Name |
Description |
|
|
tx_start |
Start of frame transmission |
|
|
tx_end |
End of frame transmission |
|
|
txResetDone |
Tx reset done |
|
|
AutoNegDone |
Auto Negotiation completed |
|
|
sgmii_TX_clk |
Transmit clock |
|
|
rx_start |
Start of frame receive |
|
|
rx_end |
End of frame receive |
|
|
rxResetDone |
Rx reset done |
|
|
AutoNegAck |
Speed Capability Autonegotiation complete |
|
|
AutoNegAckComplete |
Operational Speed acknowledge (ack) |
|
|
sa_sgmii_clk_toggle |
Generates TX/RX clocks for standalone mode ONLY |
|
Architectural Description
The SGMII eVC is made up of a stream generator, an SGMII driver, a stream monitor, an SGMII receiver, and coverage groups.
The stream generator creates streams of code groups (special and data) based on the input from a test or from a software application. It also outputs the generated streams for use by an external prediction function for the purposes of data scoreboarding.
The SGMII Driver generates 10-bit encoded data from the input stream of 8-bit code groups from the Stream Generator, serializes it and sends it out to the DUT SGMII port RX.
The SMGII Receiver deserializes SGMII data from the DUT SGMII port TX, does the 8-bit decoding and assembles the data into code group stream objects.
The Stream Monitor takes the data from the SGMII Receiver and passes it on as output to the check routine. It keeps track of important data statistics.
The Coverage block tracks the logic of the Physical Coding Sublayer (PCS) Transmit, Synchronization, PCS Receive, and Auto-Negotiation state machines as described in the SGMII to/from GMII Conversion Module Design Specification.
The SGMII eVC can serve as the interface to a PHY device or a MAC device. Both RX and TX clocks are as inputs, driven from the RTL and handled in e as events. For the configuration where the eVC acts as a PHY, this means that the testbench must supply a clock generator to control the clocks.
Simulation Core
Intrinsix has developed an GMII to SGMII Conversion Core which used the SGMII eVC for complete module level testing. The GMII to SGMII Conversion core is a Verilog component.