Sigma Delta Modulator Refinery
Sigma-Delta Modulator Refinery
The Intrinsix SDM Refinery automates this process. In the case of a DAC design, the engineer specifies an Over-Sampling Ratio (OSR), quantization levels, order of complexity and center frequency. The refinery first estimates the zero and pole locations, then optimizes the locations, estimates the Signal-to-Noise Ratio (SNR) as well as the Effective Number of Bits (ENOB) and then computes binary weighted modulator coefficients to achieve a stable, implemental modulator. In many cases, an SDM DAC can be implemented efficiently in a digital ASIC using only logic gates or with minimal off chip passive filters.
A complete data converter often needs to attenuate the aliased out-of-band frequency components from the sampling process. A DAC will often need the input interpolated (increased samples per second), while an ADC will need the output decimated (lower samples per second). The SDM Refinery is also used to generate highly computationally, efficient Poly-Phase Half-Band filters to attenuate out-of-band noise. The SDM Refinery designs the filter to a desired specification and optimizes this basic design such that it can be implemented using Conic Signed Digit (CSD) math. With CSD, each multiply of the filter is implemented using only shifts and adds. SDM Refinery tries multiple filters until it finds the optimal design that meets the design specifications with the fewest number of adders.
SDM Refinery delivers the user mathematical, behavioral and RTL-level models of the Sigma-Delta Modulator and the target Data Converter (ADC or DAC.)
Sample outputs of the SDM Refinery: