ASIC Design

Intrinsix ASIC designers are seasoned professionals with a track record in developing complex ASICs on schedule and within established budgets. We work as a team along side your own systems and ASIC developers. We refine the specifications and requirements to help assure first time success. We architect the chip for design reuse and deliver world-class synthesizable and verified designs.

For over twenty years, our growing list of satisfied customers have entrusted their designs to Intrinsix. What sets us apart is the quality and experience of each of our lead designers. Whether your designs are in terabit networking, high density mixed signal, DSP architecture or consumer electronics, we have the in-house expertise to help assure first time success in your design.

It all starts here...

Intrinsix starts its ASIC design processes with a well written system requirement document and a detailed hardware design specification. We can start with your written spec, or we can write the specifications to meet your project requirements. Writing the specifications helps our combined teams to clearly identify all of the critical aspects important to the success of the project. The rigor of writing the specification also helps define schedules and costs to a finer degree of accuracy and allows developers of sub-modules to proceed forward based on an agreed upon interface specification and verification plan.

VHDL and Verilog Expertise

Intrinsix designers have considerable expertise in both languages and have proven success in developing world-class synthesizable designs in each. Moreover, the company also has experience in the use of the Verilog PLI and the Foreign Language Interfaces to VHDL made available by Model Technology, Synopsys, Cadence and Vantage.

Synthesis and Power/Area/Speed Trade-offs

Each sub-module undergoes synthesis according to the timing budget specified for the given module. Execution speed and power consumption are directly related to the design architecture. There are occasions where circuit area can be increased to accommodate parallel logic which will allow clock rates to be slowed down resulting in a net reduction in power consumption at no loss of performance. There are other circumstances where raw speed is the ultimate concern and the hardware topology must be designed to maximize performance.

Intrinsix Principal Design Engineers understand these trade-offs and are prepared to leverage their talents on your next high-performance or low-power design project.

Physical Design and Fabrication

Intrinsix has established relationships with a number of foundries and experience in transferring gate-level designs to targeted foundries for final floor planning, physical layout and fabrication